plat_power_seq.c File Reference

#include <stdio.h>
#include <zephyr.h>
#include <logging/log.h>
#include <drivers/sensor.h>
#include <drivers/pwm.h>
#include "libutil.h"
#include "power_status.h"
#include "plat_class.h"
#include "plat_gpio.h"
#include "plat_isr.h"
#include "plat_power_seq.h"
#include "plat_mctp.h"
#include "plat_pldm_sensor.h"
#include "util_sys.h"

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Macros
#define	CXL_READY_HANDLER_STACK_SIZE   1024
#define	VR_EVENT_WAIT_BIC_RESET_DELAY_MS   (30 * 1000)

Enumerations
enum	{ HB_STATE_UNKNOWN = 0 , HB_STATE_OK , HB_STATE_LOW }

Functions
	LOG_MODULE_REGISTER (plat_power_seq)
	K_WORK_DELAYABLE_DEFINE (set_dc_on_5s_work, set_DC_on_delayed_status)
	K_WORK_DELAYABLE_DEFINE (set_cxl1_vr_ready_work, set_cxl1_vr_access_delayed_status)
	K_WORK_DELAYABLE_DEFINE (set_cxl2_vr_ready_work, set_cxl2_vr_access_delayed_status)
	K_WORK_DELAYABLE_DEFINE (cxl1_ready_thread, cxl1_ready_handler)
	K_WORK_DELAYABLE_DEFINE (cxl2_ready_thread, cxl2_ready_handler)
	K_WORK_DELAYABLE_DEFINE (cxl1_hb_monitor_work, cxl1_heartbeat_monitor_handler)
	K_WORK_DELAYABLE_DEFINE (cxl2_hb_monitor_work, cxl2_heartbeat_monitor_handler)
	K_TIMER_DEFINE (enable_asic1_rst_timer, enable_asic1_rst, NULL)
	K_TIMER_DEFINE (enable_asic2_rst_timer, enable_asic2_rst, NULL)
	K_THREAD_STACK_DEFINE (cxl1_stack_area, CXL_READY_HANDLER_STACK_SIZE)
	K_THREAD_STACK_DEFINE (cxl2_stack_area, CXL_READY_HANDLER_STACK_SIZE)
	K_MUTEX_DEFINE (switch_ioe_mux_mutex)
void	init_cxl_heartbeat_monitor_work ()
void	enable_asic1_rst ()
void	enable_asic2_rst ()
void	set_mb_dc_status (uint8_t gpio_num)
uint32_t	get_uptime_secs (void)
void	execute_power_on_sequence ()
void	create_check_cxl_ready_thread ()
int	power_on_handler (int cxl_id, int power_stage)
void	enable_powers (int cxl_id, int pwr_stage)
int	check_powers_enabled (int cxl_id, int pwr_stage)
bool	is_power_controlled (int cxl_id, int power_pin, uint8_t check_power_status, char *power_name)
void	execute_power_off_sequence ()
int	power_off_handler (int cxl_id, int power_stage)
void	disable_powers (int cxl_id, int pwr_stage)
int	check_powers_disabled (int cxl_id, int pwr_stage)
void	clear_wf_ASIC1_vr_faults ()
void	clear_wf_ASIC2_vr_faults ()
void	switch_mux_to_bic (uint8_t value_to_write)
bool	get_cxl_heartbeat (char *label)
void	cxl1_heartbeat_monitor_handler ()
void	cxl2_heartbeat_monitor_handler ()
void	cxl1_ready_handler ()
void	cxl2_ready_handler ()
void	set_cxl_vr_access (uint8_t cxl_id, bool value)
void	set_cxl1_vr_access_delayed_status ()
void	set_cxl2_vr_access_delayed_status ()
bool	cxl1_vr_access (uint8_t sensor_num)
bool	cxl2_vr_access (uint8_t sensor_num)
bool	get_cxl_vr_access_status (uint8_t cxl_id)
void	set_cxl_ready_status (uint8_t cxl_id, bool value)
bool	get_cxl_ready_status (uint8_t cxl_id)
bool	cxl1_ready_access (uint8_t sensor_num)
bool	cxl2_ready_access (uint8_t sensor_num)

Variables
struct k_thread	cxl1_thread_data
struct k_thread	cxl2_thread_data
bool	is_cxl_power_on_success = false
uint8_t	cxl1_hb_state = HB_STATE_UNKNOWN
uint8_t	cxl2_hb_state = HB_STATE_UNKNOWN
struct k_work_q	plat_work_q
cxl_power_control_gpio	cxl_power_ctrl_pin [MAX_CXL_ID]
cxl_power_good_gpio	cxl_power_good_pin [MAX_CXL_ID]
add_sel_info	cxl_event_work_items []
uint8_t	ioe_list [4]

Macro Definition Documentation

CXL_READY_HANDLER_STACK_SIZE

#define CXL_READY_HANDLER_STACK_SIZE   1024

VR_EVENT_WAIT_BIC_RESET_DELAY_MS

#define VR_EVENT_WAIT_BIC_RESET_DELAY_MS   (30 * 1000)

Enumeration Type Documentation

anonymous enum

anonymous enum

Enumerator
HB_STATE_UNKNOWN
HB_STATE_OK
HB_STATE_LOW

Function Documentation

check_powers_disabled()

int check_powers_disabled	(	int	cxl_id,
		int	pwr_stage
	)

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check_powers_enabled()

int check_powers_enabled	(	int	cxl_id,
		int	pwr_stage
	)

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clear_wf_ASIC1_vr_faults()

void clear_wf_ASIC1_vr_faults

(

)

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clear_wf_ASIC2_vr_faults()

void clear_wf_ASIC2_vr_faults

(

)

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create_check_cxl_ready_thread()

void create_check_cxl_ready_thread

(

)

cxl1_heartbeat_monitor_handler()

void cxl1_heartbeat_monitor_handler

(

)

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cxl1_ready_access()

bool cxl1_ready_access

(

uint8_t

sensor_num

)

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cxl1_ready_handler()

void cxl1_ready_handler

(

)

cxl1_vr_access()

bool cxl1_vr_access

(

uint8_t

sensor_num

)

cxl2_heartbeat_monitor_handler()

void cxl2_heartbeat_monitor_handler

(

)

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cxl2_ready_access()

bool cxl2_ready_access

(

uint8_t

sensor_num

)

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cxl2_ready_handler()

void cxl2_ready_handler

(

)

cxl2_vr_access()

bool cxl2_vr_access

(

uint8_t

sensor_num

)

disable_powers()

void disable_powers	(	int	cxl_id,
		int	pwr_stage
	)

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enable_asic1_rst()

void enable_asic1_rst

(

)

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enable_asic2_rst()

void enable_asic2_rst

(

)

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enable_powers()

void enable_powers	(	int	cxl_id,
		int	pwr_stage
	)

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execute_power_off_sequence()

void execute_power_off_sequence

(

)

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execute_power_on_sequence()

void execute_power_on_sequence

(

)

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get_cxl_heartbeat()

bool get_cxl_heartbeat

(

char *

label

)

get_cxl_ready_status()

bool get_cxl_ready_status

(

uint8_t

cxl_id

)

get_cxl_vr_access_status()

bool get_cxl_vr_access_status

(

uint8_t

cxl_id

)

get_uptime_secs()

uint32_t get_uptime_secs

(

void

)

init_cxl_heartbeat_monitor_work()

void init_cxl_heartbeat_monitor_work

(

)

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is_power_controlled()

bool is_power_controlled	(	int	cxl_id,
		int	power_pin,
		uint8_t	check_power_status,
		char *	power_name
	)

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K_MUTEX_DEFINE()

K_MUTEX_DEFINE

(

switch_ioe_mux_mutex

)

K_THREAD_STACK_DEFINE() [1/2]

K_THREAD_STACK_DEFINE	(	cxl1_stack_area	,
		CXL_READY_HANDLER_STACK_SIZE
	)

K_THREAD_STACK_DEFINE() [2/2]

K_THREAD_STACK_DEFINE	(	cxl2_stack_area	,
		CXL_READY_HANDLER_STACK_SIZE
	)

K_TIMER_DEFINE() [1/2]

K_TIMER_DEFINE	(	enable_asic1_rst_timer	,
		enable_asic1_rst	,
		NULL
	)

K_TIMER_DEFINE() [2/2]

K_TIMER_DEFINE	(	enable_asic2_rst_timer	,
		enable_asic2_rst	,
		NULL
	)

K_WORK_DELAYABLE_DEFINE() [1/7]

K_WORK_DELAYABLE_DEFINE	(	cxl1_hb_monitor_work	,
		cxl1_heartbeat_monitor_handler
	)

K_WORK_DELAYABLE_DEFINE() [2/7]

K_WORK_DELAYABLE_DEFINE	(	cxl1_ready_thread	,
		cxl1_ready_handler
	)

K_WORK_DELAYABLE_DEFINE() [3/7]

K_WORK_DELAYABLE_DEFINE	(	cxl2_hb_monitor_work	,
		cxl2_heartbeat_monitor_handler
	)

K_WORK_DELAYABLE_DEFINE() [4/7]

K_WORK_DELAYABLE_DEFINE	(	cxl2_ready_thread	,
		cxl2_ready_handler
	)

K_WORK_DELAYABLE_DEFINE() [5/7]

K_WORK_DELAYABLE_DEFINE	(	set_cxl1_vr_ready_work	,
		set_cxl1_vr_access_delayed_status
	)

K_WORK_DELAYABLE_DEFINE() [6/7]

K_WORK_DELAYABLE_DEFINE	(	set_cxl2_vr_ready_work	,
		set_cxl2_vr_access_delayed_status
	)

K_WORK_DELAYABLE_DEFINE() [7/7]

K_WORK_DELAYABLE_DEFINE	(	set_dc_on_5s_work	,
		set_DC_on_delayed_status
	)

LOG_MODULE_REGISTER()

LOG_MODULE_REGISTER

(

plat_power_seq

)

power_off_handler()

int power_off_handler	(	int	cxl_id,
		int	power_stage
	)

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power_on_handler()

int power_on_handler	(	int	cxl_id,
		int	power_stage
	)

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set_cxl1_vr_access_delayed_status()

void set_cxl1_vr_access_delayed_status

(

)

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set_cxl2_vr_access_delayed_status()

void set_cxl2_vr_access_delayed_status

(

)

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set_cxl_ready_status()

void set_cxl_ready_status	(	uint8_t	cxl_id,
		bool	value
	)

set_cxl_vr_access()

void set_cxl_vr_access	(	uint8_t	cxl_id,
		bool	value
	)

set_mb_dc_status()

void set_mb_dc_status

(

uint8_t

gpio_num

)

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switch_mux_to_bic()

void switch_mux_to_bic

(

uint8_t

value_to_write

)

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Variable Documentation

cxl1_hb_state

uint8_t cxl1_hb_state = HB_STATE_UNKNOWN

cxl1_thread_data

struct k_thread cxl1_thread_data

cxl2_hb_state

uint8_t cxl2_hb_state = HB_STATE_UNKNOWN

cxl2_thread_data

struct k_thread cxl2_thread_data

cxl_event_work_items

add_sel_info cxl_event_work_items[]

Initial value:

= {
    {
        .is_init = false,
        .assert_type = EVENT_DEASSERTED,
    },
    {
        .is_init = false,
        .assert_type = EVENT_DEASSERTED,
    },
}

cxl_power_ctrl_pin

cxl_power_control_gpio cxl_power_ctrl_pin[MAX_CXL_ID]

cxl_power_good_pin

cxl_power_good_gpio cxl_power_good_pin[MAX_CXL_ID]

Initial value:

= {
    [0] = {
    .p075v_asic_pg = PWRGD_P0V75_ASIC1,
    .p08v_asic_pg = PWRGD_P0V8_ASIC1,
    .p085v_asic_pg = PWRGD_P0V85_ASIC1,
    .p1v2_asic_pg = PWRGD_P1V2_ASIC1,
    .p1v8_asic_pg = PWRGD_P1V8_ASIC1,
    .pvpp_ab_dimm_pg = PWRGD_PVPP_AB_ASIC1,
    .pvpp_cd_dimm_pg = PWRGD_PVPP_CD_ASIC1,
    .pvddq_ab_dimm_pg = PWRGD_PVDDQ_AB_ASIC1,
    .pvddq_cd_dimm_pg = PWRGD_PVDDQ_CD_ASIC1,
    .pvtt_ab_dimm_pg = PWRGD_PVTT_AB_ASIC1,
    .pvtt_cd_dimm_pg = PWRGD_PVTT_AB_ASIC1, },
    [1] = { 
    .p075v_asic_pg = PWRGD_P0V75_ASIC2,
    .p08v_asic_pg = PWRGD_P0V8_ASIC2,
    .p085v_asic_pg = PWRGD_P0V85_ASIC2,
    .p1v2_asic_pg = PWRGD_P1V2_ASIC2,
    .p1v8_asic_pg = PWRGD_P1V8_ASIC2,
    .pvpp_ab_dimm_pg = PWRGD_PVPP_AB_ASIC2,
    .pvpp_cd_dimm_pg = PWRGD_PVPP_CD_ASIC2,
    .pvddq_ab_dimm_pg = PWRGD_PVDDQ_AB_ASIC2,
    .pvddq_cd_dimm_pg = PWRGD_PVDDQ_CD_ASIC2,
    .pvtt_ab_dimm_pg = PWRGD_PVTT_AB_ASIC2,
    .pvtt_cd_dimm_pg = PWRGD_PVTT_AB_ASIC2, },
}

ioe_list

uint8_t ioe_list[4]

extern

is_cxl_power_on_success

bool is_cxl_power_on_success = false

plat_work_q

struct k_work_q plat_work_q

extern