#include <stdio.h>#include <zephyr.h>#include <logging/log.h>#include <drivers/sensor.h>#include <drivers/pwm.h>#include "libutil.h"#include "power_status.h"#include "plat_class.h"#include "plat_gpio.h"#include "plat_isr.h"#include "plat_power_seq.h"
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Macros | |
| #define | CXL_READY_HANDLER_STACK_SIZE 1024 |
Variables | |
| struct k_thread | cxl1_thread_data |
| struct k_thread | cxl2_thread_data |
| cxl_power_control_gpio | cxl_power_ctrl_pin [MAX_CXL_ID] |
| cxl_power_good_gpio | cxl_power_good_pin [MAX_CXL_ID] |
Macro Definition Documentation
◆ CXL_READY_HANDLER_STACK_SIZE
| #define CXL_READY_HANDLER_STACK_SIZE 1024 |
Function Documentation
◆ check_powers_disabled()
| int check_powers_disabled | ( | int | cxl_id, |
| int | pwr_stage | ||
| ) |
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◆ check_powers_enabled()
| int check_powers_enabled | ( | int | cxl_id, |
| int | pwr_stage | ||
| ) |
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◆ create_check_cxl_ready_thread()
| void create_check_cxl_ready_thread | ( | ) |
◆ cxl1_ready_access()
| bool cxl1_ready_access | ( | uint8_t | sensor_num | ) |
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◆ cxl1_ready_handler()
| void cxl1_ready_handler | ( | ) |
◆ cxl1_vr_access()
| bool cxl1_vr_access | ( | uint8_t | sensor_num | ) |
◆ cxl2_ready_access()
| bool cxl2_ready_access | ( | uint8_t | sensor_num | ) |
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◆ cxl2_ready_handler()
| void cxl2_ready_handler | ( | ) |
◆ cxl2_vr_access()
| bool cxl2_vr_access | ( | uint8_t | sensor_num | ) |
◆ disable_powers()
| void disable_powers | ( | int | cxl_id, |
| int | pwr_stage | ||
| ) |
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◆ enable_asic1_rst()
| void enable_asic1_rst | ( | ) |
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◆ enable_asic2_rst()
| void enable_asic2_rst | ( | ) |
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◆ enable_powers()
| void enable_powers | ( | int | cxl_id, |
| int | pwr_stage | ||
| ) |
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◆ execute_power_off_sequence()
| void execute_power_off_sequence | ( | ) |
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◆ execute_power_on_sequence()
| void execute_power_on_sequence | ( | ) |
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◆ get_cxl_ready_status()
| bool get_cxl_ready_status | ( | uint8_t | cxl_id | ) |
◆ is_power_controlled()
| bool is_power_controlled | ( | int | cxl_id, |
| int | power_pin, | ||
| uint8_t | check_power_status, | ||
| char * | power_name | ||
| ) |
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◆ K_MUTEX_DEFINE()
| K_MUTEX_DEFINE | ( | switch_ioe_mux_mutex | ) |
◆ K_THREAD_STACK_DEFINE() [1/2]
| K_THREAD_STACK_DEFINE | ( | cxl1_stack_area | , |
| CXL_READY_HANDLER_STACK_SIZE | |||
| ) |
◆ K_THREAD_STACK_DEFINE() [2/2]
| K_THREAD_STACK_DEFINE | ( | cxl2_stack_area | , |
| CXL_READY_HANDLER_STACK_SIZE | |||
| ) |
◆ K_WORK_DELAYABLE_DEFINE() [1/7]
| K_WORK_DELAYABLE_DEFINE | ( | cxl1_ready_thread | , |
| cxl1_ready_handler | |||
| ) |
◆ K_WORK_DELAYABLE_DEFINE() [2/7]
| K_WORK_DELAYABLE_DEFINE | ( | cxl2_ready_thread | , |
| cxl2_ready_handler | |||
| ) |
◆ K_WORK_DELAYABLE_DEFINE() [3/7]
| K_WORK_DELAYABLE_DEFINE | ( | enable_asic1_rst_work | , |
| enable_asic1_rst | |||
| ) |
◆ K_WORK_DELAYABLE_DEFINE() [4/7]
| K_WORK_DELAYABLE_DEFINE | ( | enable_asic2_rst_work | , |
| enable_asic2_rst | |||
| ) |
◆ K_WORK_DELAYABLE_DEFINE() [5/7]
| K_WORK_DELAYABLE_DEFINE | ( | set_cxl1_vr_ready_work | , |
| set_cxl1_vr_access_delayed_status | |||
| ) |
◆ K_WORK_DELAYABLE_DEFINE() [6/7]
| K_WORK_DELAYABLE_DEFINE | ( | set_cxl2_vr_ready_work | , |
| set_cxl2_vr_access_delayed_status | |||
| ) |
◆ K_WORK_DELAYABLE_DEFINE() [7/7]
| K_WORK_DELAYABLE_DEFINE | ( | set_dc_on_5s_work | , |
| set_DC_on_delayed_status | |||
| ) |
◆ LOG_MODULE_REGISTER()
| LOG_MODULE_REGISTER | ( | plat_power_seq | ) |
◆ power_off_handler()
| int power_off_handler | ( | int | cxl_id, |
| int | power_stage | ||
| ) |
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◆ power_on_handler()
| int power_on_handler | ( | int | cxl_id, |
| int | power_stage | ||
| ) |
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◆ set_cxl1_vr_access_delayed_status()
| void set_cxl1_vr_access_delayed_status | ( | ) |
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◆ set_cxl2_vr_access_delayed_status()
| void set_cxl2_vr_access_delayed_status | ( | ) |
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◆ set_cxl_ready_status()
| void set_cxl_ready_status | ( | uint8_t | cxl_id, |
| bool | value | ||
| ) |
◆ set_cxl_vr_access()
| void set_cxl_vr_access | ( | uint8_t | cxl_id, |
| bool | value | ||
| ) |
◆ set_mb_dc_status()
| void set_mb_dc_status | ( | uint8_t | gpio_num | ) |
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◆ switch_mux_to_bic()
| void switch_mux_to_bic | ( | uint8_t | value_to_write | ) |
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Variable Documentation
◆ cxl1_thread_data
| struct k_thread cxl1_thread_data |
◆ cxl2_thread_data
| struct k_thread cxl2_thread_data |
◆ cxl_power_ctrl_pin
| cxl_power_control_gpio cxl_power_ctrl_pin[MAX_CXL_ID] |
◆ cxl_power_good_pin
| cxl_power_good_gpio cxl_power_good_pin[MAX_CXL_ID] |
Initial value:
= {
[0] = {
.p075v_asic_pg = PWRGD_P0V75_ASIC1,
.p08v_asic_pg = PWRGD_P0V8_ASIC1,
.p085v_asic_pg = PWRGD_P0V85_ASIC1,
.p1v2_asic_pg = PWRGD_P1V2_ASIC1,
.p1v8_asic_pg = PWRGD_P1V8_ASIC1,
.pvpp_ab_dimm_pg = PWRGD_PVPP_AB_ASIC1,
.pvpp_cd_dimm_pg = PWRGD_PVPP_CD_ASIC1,
.pvddq_ab_dimm_pg = PWRGD_PVDDQ_AB_ASIC1,
.pvddq_cd_dimm_pg = PWRGD_PVDDQ_CD_ASIC1,
.pvtt_ab_dimm_pg = PWRGD_PVTT_AB_ASIC1,
.pvtt_cd_dimm_pg = PWRGD_PVTT_AB_ASIC1, },
[1] = {
.p075v_asic_pg = PWRGD_P0V75_ASIC2,
.p08v_asic_pg = PWRGD_P0V8_ASIC2,
.p085v_asic_pg = PWRGD_P0V85_ASIC2,
.p1v2_asic_pg = PWRGD_P1V2_ASIC2,
.p1v8_asic_pg = PWRGD_P1V8_ASIC2,
.pvpp_ab_dimm_pg = PWRGD_PVPP_AB_ASIC2,
.pvpp_cd_dimm_pg = PWRGD_PVPP_CD_ASIC2,
.pvddq_ab_dimm_pg = PWRGD_PVDDQ_AB_ASIC2,
.pvddq_cd_dimm_pg = PWRGD_PVDDQ_CD_ASIC2,
.pvtt_ab_dimm_pg = PWRGD_PVTT_AB_ASIC2,
.pvtt_cd_dimm_pg = PWRGD_PVTT_AB_ASIC2, },
}
