Go to the source code of this file.
|
| enum | CXL_NUM { CXL_ID_1 = 0
, CXL_ID_2
, MAX_CXL_ID
} |
| |
| enum | POWER_ON_STAGE {
BOARD_POWER_ON_STAGE0 = 0x00
, BOARD_POWER_ON_STAGE1
, BOARD_POWER_ON_STAGE2
, RETIMER_POWER_ON_STAGE0
,
RETIMER_POWER_ON_STAGE1
, RETIMER_POWER_ON_STAGE2
, E1S_POWER_ON_STAGE0
, E1S_POWER_ON_STAGE1
,
E1S_POWER_ON_STAGE2
, E1S_POWER_ON_STAGE3
, ASIC_POWER_ON_STAGE1 = 0x00
, ASIC_POWER_ON_STAGE2
,
DIMM_POWER_ON_STAGE1
, DIMM_POWER_ON_STAGE2
, DIMM_POWER_ON_STAGE3
, ASIC_POWER_ON_STAGE = 0x00
,
DIMM_POWER_ON_STAGE1
, DIMM_POWER_ON_STAGE2
, DIMM_POWER_ON_STAGE3
, BOARD_POWER_ON_STAGE
,
CLK_POWER_ON_STAGE = 0
, ASIC_POWER_ON_STAGE_1
, ASIC_POWER_ON_STAGE_2
, DIMM_POWER_ON_STAGE_1
,
DIMM_POWER_ON_STAGE_2
, DIMM_POWER_ON_STAGE_3
, MAX_POWER_ON_STAGES
, ASIC_POWER_ON_STAGE_1 = 0
,
CLK_POWER_ON_STAGE
, ASIC_POWER_ON_STAGE_2
, ASIC_POWER_ON_STAGE_3
, DIMM_POWER_ON_STAGE_1
,
DIMM_POWER_ON_STAGE_2
, DIMM_POWER_ON_STAGE_3
, MAX_POWER_ON_STAGES
} |
| |
| enum | POWER_OFF_STAGE {
E1S_POWER_OFF_STAGE0 = 0x00
, E1S_POWER_OFF_STAGE1
, E1S_POWER_OFF_STAGE2
, E1S_POWER_OFF_STAGE3
,
RETIMER_POWER_OFF_STAGE0
, RETIMER_POWER_OFF_STAGE1
, RETIMER_POWER_OFF_STAGE2
, BOARD_POWER_OFF_STAGE0
,
BOARD_POWER_OFF_STAGE1
, BOARD_POWER_OFF_STAGE2
, DIMM_POWER_OFF_STAGE1 = 0x00
, DIMM_POWER_OFF_STAGE2
,
DIMM_POWER_OFF_STAGE3
, ASIC_POWER_OFF_STAGE1
, ASIC_POWER_OFF_STAGE2
, BOARD_POWER_OFF_STAGE
,
DIMM_POWER_OFF_STAGE1 = 0x00
, DIMM_POWER_OFF_STAGE2
, DIMM_POWER_OFF_STAGE3
, ASIC_POWER_OFF_STAGE1
,
ASIC_POWER_OFF_STAGE2
, BOARD_POWER_OFF_STAGE
, DIMM_POWER_OFF_STAGE_1 = 0
, DIMM_POWER_OFF_STAGE_2
,
DIMM_POWER_OFF_STAGE_3
, ASIC_POWER_OFF_STAGE_1
, ASIC_POWER_OFF_STAGE_2
, ASIC_POWER_OFF_STAGE_3
,
CLK_POWER_OFF_STAGE
, MAX_POWER_OFF_STAGES
, DIMM_POWER_OFF_STAGE_1 = 0
, DIMM_POWER_OFF_STAGE_2
,
DIMM_POWER_OFF_STAGE_3
, ASIC_POWER_OFF_STAGE_1
, ASIC_POWER_OFF_STAGE_2
, ASIC_POWER_OFF_STAGE_3
,
CLK_POWER_OFF_STAGE
, MAX_POWER_OFF_STAGES
} |
| |
|
| void | set_mb_dc_status (uint8_t gpio_num) |
| |
| void | enable_asic1_rst () |
| |
| void | enable_asic2_rst () |
| |
| bool | is_power_controlled (int cxl_id, int power_pin, uint8_t check_power_status, char *power_name) |
| |
| int | check_powers_enabled (int cxl_id, int pwr_stage) |
| |
| int | check_powers_disabled (int cxl_id, int pwr_stage) |
| |
| void | enable_powers (int cxl_id, int pwr_stage) |
| |
| void | disable_powers (int cxl_id, int pwr_stage) |
| |
| int | power_on_handler (int cxl_id, int power_stage) |
| |
| int | power_off_handler (int cxl_id, int power_stage) |
| |
| void | execute_power_on_sequence () |
| |
| void | execute_power_off_sequence () |
| |
| void | cxl1_ready_handler () |
| |
| void | cxl2_ready_handler () |
| |
| void | set_cxl_ready_status (uint8_t cxl_id, bool value) |
| |
| bool | get_cxl_ready_status (uint8_t cxl_id) |
| |
| bool | cxl1_ready_access (uint8_t sensor_num) |
| |
| bool | cxl2_ready_access (uint8_t sensor_num) |
| |
| void | set_cxl_vr_access (uint8_t cxl_id, bool value) |
| |
| void | set_cxl1_vr_access_delayed_status () |
| |
| void | set_cxl2_vr_access_delayed_status () |
| |
| bool | cxl1_vr_access (uint8_t sensor_num) |
| |
| bool | cxl2_vr_access (uint8_t sensor_num) |
| |
| void | create_check_cxl_ready_thread () |
| |
| bool | get_cxl_heartbeat (char *label) |
| |
| void | cxl1_heartbeat_monitor_handler () |
| |
| void | cxl2_heartbeat_monitor_handler () |
| |
| void | init_cxl_heartbeat_monitor_work () |
| |
| void | plat_pldm_sensor_clear_vr_fault (uint8_t vr_addr, uint8_t vr_bus, uint8_t page_cnt) |
| |
| void | switch_mux_to_bic (uint8_t value_to_write) |
| |
| bool | get_cxl_vr_access_status (uint8_t cxl_id) |
| |
◆ CHK_PWR_DELAY_MSEC
| #define CHK_PWR_DELAY_MSEC 1 |
◆ CXL1_HEART_BEAT_LABEL
| #define CXL1_HEART_BEAT_LABEL "HB0" |
◆ CXL2_HEART_BEAT_LABEL
| #define CXL2_HEART_BEAT_LABEL "HB1" |
◆ CXL_READY_INTERVAL_SECONDS
| #define CXL_READY_INTERVAL_SECONDS 3 |
◆ CXL_READY_RETRY_TIMES
| #define CXL_READY_RETRY_TIMES 50 |
◆ CXL_READY_SECONDS
| #define CXL_READY_SECONDS 30 |
◆ DC_ON_DELAY5_SEC
| #define DC_ON_DELAY5_SEC 5 |
◆ MONITOR_INTERVAL_SECONDS
| #define MONITOR_INTERVAL_SECONDS 10 |
◆ P1V8_POWER_OFF_DELAY_MSEC
| #define P1V8_POWER_OFF_DELAY_MSEC 3500 |
◆ POWER_SEQ_CTRL_STACK_SIZE
| #define POWER_SEQ_CTRL_STACK_SIZE 1000 |
◆ PWR_RST_DELAY_MSEC
| #define PWR_RST_DELAY_MSEC 25 |
◆ SWITCH_IOE_MUX_TIMEOUT_SECONDS
| #define SWITCH_IOE_MUX_TIMEOUT_SECONDS 1 |
◆ SYS_CLK_STABLE_DELAY_MSEC
| #define SYS_CLK_STABLE_DELAY_MSEC 25 |
◆ VR_READY_DELAY_SEC
| #define VR_READY_DELAY_SEC 7 |
◆ add_sel_info
◆ cxl_power_control_gpio
◆ cxl_power_good_gpio
◆ CXL_NUM
| Enumerator |
|---|
| CXL_ID_1 | |
| CXL_ID_2 | |
| MAX_CXL_ID | |
◆ POWER_OFF_STAGE
| Enumerator |
|---|
| E1S_POWER_OFF_STAGE0 | |
| E1S_POWER_OFF_STAGE1 | |
| E1S_POWER_OFF_STAGE2 | |
| E1S_POWER_OFF_STAGE3 | |
| RETIMER_POWER_OFF_STAGE0 | |
| RETIMER_POWER_OFF_STAGE1 | |
| RETIMER_POWER_OFF_STAGE2 | |
| BOARD_POWER_OFF_STAGE0 | |
| BOARD_POWER_OFF_STAGE1 | |
| BOARD_POWER_OFF_STAGE2 | |
| DIMM_POWER_OFF_STAGE1 | |
| DIMM_POWER_OFF_STAGE2 | |
| DIMM_POWER_OFF_STAGE3 | |
| ASIC_POWER_OFF_STAGE1 | |
| ASIC_POWER_OFF_STAGE2 | |
| BOARD_POWER_OFF_STAGE | |
| DIMM_POWER_OFF_STAGE1 | |
| DIMM_POWER_OFF_STAGE2 | |
| DIMM_POWER_OFF_STAGE3 | |
| ASIC_POWER_OFF_STAGE1 | |
| ASIC_POWER_OFF_STAGE2 | |
| BOARD_POWER_OFF_STAGE | |
| DIMM_POWER_OFF_STAGE_1 | |
| DIMM_POWER_OFF_STAGE_2 | |
| DIMM_POWER_OFF_STAGE_3 | |
| ASIC_POWER_OFF_STAGE_1 | |
| ASIC_POWER_OFF_STAGE_2 | |
| ASIC_POWER_OFF_STAGE_3 | |
| CLK_POWER_OFF_STAGE | |
| MAX_POWER_OFF_STAGES | |
| DIMM_POWER_OFF_STAGE_1 | |
| DIMM_POWER_OFF_STAGE_2 | |
| DIMM_POWER_OFF_STAGE_3 | |
| ASIC_POWER_OFF_STAGE_1 | |
| ASIC_POWER_OFF_STAGE_2 | |
| ASIC_POWER_OFF_STAGE_3 | |
| CLK_POWER_OFF_STAGE | |
| MAX_POWER_OFF_STAGES | |
◆ POWER_ON_STAGE
| Enumerator |
|---|
| BOARD_POWER_ON_STAGE0 | |
| BOARD_POWER_ON_STAGE1 | |
| BOARD_POWER_ON_STAGE2 | |
| RETIMER_POWER_ON_STAGE0 | |
| RETIMER_POWER_ON_STAGE1 | |
| RETIMER_POWER_ON_STAGE2 | |
| E1S_POWER_ON_STAGE0 | |
| E1S_POWER_ON_STAGE1 | |
| E1S_POWER_ON_STAGE2 | |
| E1S_POWER_ON_STAGE3 | |
| ASIC_POWER_ON_STAGE1 | |
| ASIC_POWER_ON_STAGE2 | |
| DIMM_POWER_ON_STAGE1 | |
| DIMM_POWER_ON_STAGE2 | |
| DIMM_POWER_ON_STAGE3 | |
| ASIC_POWER_ON_STAGE | |
| DIMM_POWER_ON_STAGE1 | |
| DIMM_POWER_ON_STAGE2 | |
| DIMM_POWER_ON_STAGE3 | |
| BOARD_POWER_ON_STAGE | |
| CLK_POWER_ON_STAGE | |
| ASIC_POWER_ON_STAGE_1 | |
| ASIC_POWER_ON_STAGE_2 | |
| DIMM_POWER_ON_STAGE_1 | |
| DIMM_POWER_ON_STAGE_2 | |
| DIMM_POWER_ON_STAGE_3 | |
| MAX_POWER_ON_STAGES | |
| ASIC_POWER_ON_STAGE_1 | |
| CLK_POWER_ON_STAGE | |
| ASIC_POWER_ON_STAGE_2 | |
| ASIC_POWER_ON_STAGE_3 | |
| DIMM_POWER_ON_STAGE_1 | |
| DIMM_POWER_ON_STAGE_2 | |
| DIMM_POWER_ON_STAGE_3 | |
| MAX_POWER_ON_STAGES | |
◆ check_powers_disabled()
| int check_powers_disabled |
( |
int |
cxl_id, |
|
|
int |
pwr_stage |
|
) |
| |
◆ check_powers_enabled()
| int check_powers_enabled |
( |
int |
cxl_id, |
|
|
int |
pwr_stage |
|
) |
| |
◆ create_check_cxl_ready_thread()
| void create_check_cxl_ready_thread |
( |
| ) |
|
◆ cxl1_heartbeat_monitor_handler()
| void cxl1_heartbeat_monitor_handler |
( |
| ) |
|
◆ cxl1_ready_access()
| bool cxl1_ready_access |
( |
uint8_t |
sensor_num | ) |
|
◆ cxl1_ready_handler()
| void cxl1_ready_handler |
( |
| ) |
|
◆ cxl1_vr_access()
| bool cxl1_vr_access |
( |
uint8_t |
sensor_num | ) |
|
◆ cxl2_heartbeat_monitor_handler()
| void cxl2_heartbeat_monitor_handler |
( |
| ) |
|
◆ cxl2_ready_access()
| bool cxl2_ready_access |
( |
uint8_t |
sensor_num | ) |
|
◆ cxl2_ready_handler()
| void cxl2_ready_handler |
( |
| ) |
|
◆ cxl2_vr_access()
| bool cxl2_vr_access |
( |
uint8_t |
sensor_num | ) |
|
◆ disable_powers()
| void disable_powers |
( |
int |
cxl_id, |
|
|
int |
pwr_stage |
|
) |
| |
◆ enable_asic1_rst()
| void enable_asic1_rst |
( |
| ) |
|
◆ enable_asic2_rst()
| void enable_asic2_rst |
( |
| ) |
|
◆ enable_powers()
| void enable_powers |
( |
int |
cxl_id, |
|
|
int |
pwr_stage |
|
) |
| |
◆ execute_power_off_sequence()
| void execute_power_off_sequence |
( |
| ) |
|
◆ execute_power_on_sequence()
| void execute_power_on_sequence |
( |
| ) |
|
◆ get_cxl_heartbeat()
| bool get_cxl_heartbeat |
( |
char * |
label | ) |
|
◆ get_cxl_ready_status()
| bool get_cxl_ready_status |
( |
uint8_t |
cxl_id | ) |
|
◆ get_cxl_vr_access_status()
| bool get_cxl_vr_access_status |
( |
uint8_t |
cxl_id | ) |
|
◆ init_cxl_heartbeat_monitor_work()
| void init_cxl_heartbeat_monitor_work |
( |
| ) |
|
◆ is_power_controlled()
| bool is_power_controlled |
( |
int |
cxl_id, |
|
|
int |
power_pin, |
|
|
uint8_t |
check_power_status, |
|
|
char * |
power_name |
|
) |
| |
◆ plat_pldm_sensor_clear_vr_fault()
| void plat_pldm_sensor_clear_vr_fault |
( |
uint8_t |
vr_addr, |
|
|
uint8_t |
vr_bus, |
|
|
uint8_t |
page_cnt |
|
) |
| |
◆ power_off_handler()
| int power_off_handler |
( |
int |
cxl_id, |
|
|
int |
power_stage |
|
) |
| |
◆ power_on_handler()
| int power_on_handler |
( |
int |
cxl_id, |
|
|
int |
power_stage |
|
) |
| |
◆ set_cxl1_vr_access_delayed_status()
| void set_cxl1_vr_access_delayed_status |
( |
| ) |
|
◆ set_cxl2_vr_access_delayed_status()
| void set_cxl2_vr_access_delayed_status |
( |
| ) |
|
◆ set_cxl_ready_status()
| void set_cxl_ready_status |
( |
uint8_t |
cxl_id, |
|
|
bool |
value |
|
) |
| |
◆ set_cxl_vr_access()
| void set_cxl_vr_access |
( |
uint8_t |
cxl_id, |
|
|
bool |
value |
|
) |
| |
◆ set_mb_dc_status()
| void set_mb_dc_status |
( |
uint8_t |
gpio_num | ) |
|
◆ switch_mux_to_bic()
| void switch_mux_to_bic |
( |
uint8_t |
value_to_write | ) |
|