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pldm_oem.h File Reference
#include "pldm.h"
#include <stdint.h>
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Classes

struct  _cmd_echo_req
 
struct  _cmd_echo_resp
 
struct  _ipmi_cmd_req
 
struct  _ipmi_cmd_resp
 
struct  pldm_oem_write_file_io_req
 
struct  pldm_oem_write_file_io_resp
 
struct  pldm_oem_read_file_data_info
 
struct  pldm_oem_read_file_attr_info
 
struct  pldm_oem_read_file_io_attr_req
 
struct  pldm_oem_read_file_io_data_req
 
struct  pldm_oem_read_file_io_attr_resp
 
struct  pldm_oem_read_file_io_data_resp
 
struct  pldm_addsel_data
 
struct  _sensor_polling_cmd_req
 
struct  _sensor_polling_cmd_resp
 
struct  _force_update_flag_set_cmd_req
 
struct  _force_update_flag_set_cmd_resp
 
struct  _force_update_flag_get_cmd_req
 
struct  _force_update_flag_get_cmd_resp
 

Macros

#define IANA_LEN   0x03
 
#define OEM_EVENT_LEN   0x05
 
#define EVENT_ASSERTED   0x01
 
#define EVENT_DEASSERTED   0x00
 
#define PLDM_OEM_CMD_ECHO   0x00
 
#define PLDM_OEM_IPMI_BRIDGE   0x01
 
#define PLDM_OEM_WRITE_FILE_IO   0x02
 
#define PLDM_OEM_READ_FILE_IO   0x03
 
#define PLDM_OEM_SENSOR_POLLING_CMD   0x04
 
#define PLDM_OEM_WF_READ_SPD_CHUNK   0x05
 
#define PLDM_OEM_FORCE_UPDATE_SETTING_CMD   0x06
 
#define PLDM_OEM_FORCE_UPDATE_GETTING_CMD   0x07
 
#define POWER_CONTROL_LEN   0x01
 

Enumerations

enum  cmd_type {
  POST_CODE = 0x00 , BIOS_VERSION = 0x01 , POWER_CONTROL = 0x02 , HTTP_BOOT = 0X03 ,
  APML_ALERT = 0x04 , EVENT_LOG = 0x05 , CRASH_DUMP = 0x06 , BOOT_ORDER = 0x07
}
 
enum  POWER_CONTROL_OPTION {
  SLED_CYCLE = 0x00 , SLOT_12V_CYCLE = 0x01 , SLOT_DC_CYCLE = 0x02 , NIC0_POWER_CYCLE = 0x03 ,
  NIC1_POWER_CYCLE = 0x04 , NIC2_POWER_CYCLE = 0x05 , NIC3_POWER_CYCLE = 0x06 , MAX_POWER_OPTION
}
 
enum  oem_event_type {
  CPU_THERMAL_TRIP = 0x00 , HSC_OCP , P12V_STBY_UV , PMALERT_ASSERT ,
  FAST_PROCHOT_ASSERT , FRB3_TIMER_EXPIRE , POWER_ON_SEQUENCE_FAIL , DIMM_PMIC_ERROR ,
  ADDC_DUMP , BMC_COMES_OUT_COLD_RESET , BIOS_FRB2_WDT_EXPIRE , BIC_POWER_FAIL ,
  CPU_POWER_FAIL , BMC_VBOOT_FAIL , BMC_REBOOT_REQUESTED , CHASSIS_POWER_ON_BY_NIC_INSERT ,
  BLADE_POWER_CYCLE_BY_BLADE_BTN , CHASSIS_POWER_CYCLE_BY_SLED_BTN , HSC_FAULT , SYS_THROTTLE ,
  VR_FAULT , SYS_MANAGEMENT_ERROR , POST_COMPLETED , FAN_ERROR ,
  HDT_PRSNT_ASSERT , PLTRST_ASSERT , APML_ALERT_ASSERT , CXL1_HB ,
  CXL2_HB , POST_STARTED , POST_ENDED , PROCHOT_TRIGGERED_BY_SENSOR_UCR ,
  FRB2_WDT_HARD_RST , FRB2_WDT_PWR_DOWN , FRB2_WDT_PWR_CYCLE , OS_LOAD_WDT_EXPIRED ,
  OS_LOAD_WDT_HARD_RST , OS_LOAD_WDT_PWR_DOWN , OS_LOAD_WDT_PWR_CYCLE , MTIA_FAULT ,
  POST_TIMEOUTED , IRIS_FAULT , ARKE_FAULT
}
 
enum  vr_event_source {
  PVDDCR_CPU0 = 0x00 , PVDDCR_SOC , PVDDCR_CPU1 , PVDDIO ,
  PVDD11_S3 , PVDDQ_AB_ASIC1 , P0V85_ASIC1 , PVDDQ_CD_ASIC1 ,
  P0V8_ASIC1 , PVDDQ_AB_ASIC2 , P0V85_ASIC2 , PVDDQ_CD_ASIC2 ,
  P0V8_ASIC2 , P1V5_RETIMER_1 , P0V9_STBY_1 , P3V3_E1S_0 ,
  P3V3_E1S_1 , P12V_E1S_0 , P12V_E1S_1 , PVTT_AB_ASIC1 ,
  PVTT_AB_ASIC2 , PVTT_CD_ASIC1 , PVTT_CD_ASIC2 , PVPP_AB_ASIC1 ,
  PVPP_AB_ASIC2 , PVPP_CD_ASIC1 , PVPP_CD_ASIC2
}
 
enum  mtia_event_source {
  MTIA_P3V3 = 0 , MTIA_P0V85_PVDD , MTIA_P0V75_PVDD_CH_N , MTIA_P0V75_MAX_PHY_N ,
  MTIA_P0V75_PVDD_CH_S , MTIA_P0V75_MAX_PHY_S , MTIA_P0V75_TRVDD_ZONEA , MTIA_P1V8_VPP_HBM0_HBM2_HBM4 ,
  MTIA_P0V75_TRVDD_ZONEB , MTIA_P0V4_VDDQL_HBM0_HBM2_HBM4 , MTIA_P1V1_VDDC_HBM0_HBM2_HBM4 , MTIA_P0V75_VDDPHY_HBM0_HBM2_HBM4 ,
  MTIA_P0V9_TRVDD_ZONEA , MTIA_P1V8_VPP_HBM1_HBM3_HBM5 , MTIA_P0V9_TRVDD_ZONEB , MTIA_P0V4_VDDQL_HBM1_HBM3_HBM5 ,
  MTIA_P1V1_VDDC_HBM1_HBM3_HBM5 , MTIA_P0V75_VDDPHY_HBM1_HBM3_HBM5 , MTIA_P0V8_VDDA_PCIE , MTIA_P1V2_VDDHTX_PCIE ,
  MTIA_P12V_UBC1 , MTIA_P12V_UBC2 , MTIA_VR_MAX , MTIA_PLL_VDDA15_PCIE_MAX_CORE = 0x30 ,
  MTIA_P0V75_AVDD_HSCL , MTIA_P0V75_VDDC_CLKOBS , MTIA_PLL_VDDA15_MAX_CORE_N , MTIA_PVDD1P5_S ,
  MTIA_PVDD1P5_N , MTIA_PVDD0P9_S , MTIA_PVDD0P9_N , MTIA_PLL_VDDA15_HBM0_HBM2_HBM4 ,
  MTIA_PLL_VDDA15_HBM1_HBM3_HBM5 , MTIA_P3V3_OSC , MTIA_P5V , MTIA_LDO_IN_1V8 ,
  MTIA_LDO_IN_1V2 , MTIA_PLL_VDDA15_MAX_CORE_S , MTIA_POWER_ON_SEQUENCE_FAIL = 0x50 , MTIA_FM_ASIC_0_THERMTRIP_N ,
  MTIA_FM_ATH_PLD_HBM3_CATTRIP_ALARM , MTIA_VR_FAULT_CAUSE_POWER_DOWN , MTIA_ATH_GPIO_3 , MTIA_ATH_GPIO_4
}
 
enum  iris_event_source {
  IRIS_HAMSA_VDDHRXTX_PCIE = 0 , IRIS_HAMSA_AVDD_PCIE , IRIS_OWL_W_TRVDD0P75 , IRIS_OWL_E_TRVDD0P75 ,
  IRIS_OWL_W_TRVDD0P9 , IRIS_OWL_E_TRVDD0P9 , IRIS_MAX_N_VDD , IRIS_MAX_M_VDD ,
  IRIS_MAX_S_VDD , IRIS_HAMSA_VDD , IRIS_OWL_W_VDD , IRIS_OWL_E_VDD ,
  IRIS_MEDHA0_VDD , IRIS_MEDHA1_VDD , IRIS_VDDPHY_HBM1_HBM3_HBM5_HBM7 , IRIS_VPP_HBM1_HBM3_HBM5_HBM7 ,
  IRIS_VDDQC_HBM1_HBM3_HBM5_HBM7 , IRIS_VDDQL_HBM1_HBM3_HBM5_HBM7 , IRIS_VDDPHY_HBM0_HBM2_HBM4_HBM6 , IRIS_VPP_HBM0_HBM2_HBM4_HBM6 ,
  IRIS_VDDQC_HBM0_HBM2_HBM4_HBM6 , IRIS_VDDQL_HBM0_HBM2_HBM4_HBM6 , IRIS_P1V5_W_RVDD , IRIS_P1V5_E_RVDD ,
  IRIS_P0V9_OWL_W_PVDD , IRIS_P0V9_OWL_E_PVDD , IRIS_PLL_VDDA15_HBM5_HBM7 , IRIS_PLL_VDDA15_HBM1_HBM3 ,
  IRIS_PLL_VDDA15_HBM4_HBM6 , IRIS_PLL_VDDA15_HBM0_HBM2 , IRIS_PVDD1P5 , IRIS_P1V5_PLL_VDDA_SOC ,
  IRIS_P1V5_PLL_VDDA_OWL , IRIS_LDO_IN_1V2 , IRIS_P1V8 , IRIS_P3V3 ,
  IRIS_P5V , IRIS_P12V_UBC_PWRGD , IRIS_P0V75_AVDD_HCSL , IRIS_4V2 ,
  IRIS_MAX_N_VDDRXTX_SMBALRT_N = 0x31 , IRIS_VDDQC_VDDQL_0246_SMBALRT_N , IRIS_MAX_M_VDDQC_1357_SMBALRT_N , IRIS_OWL_W_SMBALRT_N ,
  IRIS_OWL_E_SMBALRT_N , IRIS_MEDHA1_VDD_ALERT_R_N , IRIS_MEDHA0_VDD_ALERT_R_N , IRIS_POWER_ON_SEQUENCE_FAIL = 0x50 ,
  IRIS_ASIC_THERMTRIP , IRIS_MEDHA1_HBM_CATTRIP , IRIS_MEDHA0_HBM_CATTRIP
}
 
enum  arke_event_source {
  ARKE_HAMSA_VDDHRXTX_PCIE = 0 , ARKE_HAMSA_AVDD_PCIE , ARKE_OWL_W_TRVDD0P75 , ARKE_OWL_E_TRVDD0P75 ,
  ARKE_OWL_W_TRVDD0P9 , ARKE_OWL_E_TRVDD0P9 , ARKE_MAX_N_VDD , ARKE_MAX_M_VDD ,
  ARKE_MAX_S_VDD , ARKE_HAMSA_VDD , ARKE_OWL_W_VDD , ARKE_OWL_E_VDD ,
  ARKE_NUWA0_VDD , ARKE_NUWA1_VDD , ARKE_VDDPHY_HBM1_HBM3_HBM5_HBM7 , ARKE_VPP_HBM1_HBM3_HBM5_HBM7 ,
  ARKE_VDDC_HBM1_HBM3_HBM5_HBM7 , ARKE_VDDQL_HBM1_HBM3_HBM5_HBM7 , ARKE_VDDPHY_HBM0_HBM2_HBM4_HBM6 , ARKE_VPP_HBM0_HBM2_HBM4_HBM6 ,
  ARKE_VDDC_HBM0_HBM2_HBM4_HBM6 , ARKE_VDDQL_HBM0_HBM2_HBM4_HBM6 , ARKE_P1V5_W_RVDD , ARKE_P1V5_E_RVDD ,
  ARKE_P0V9_OWL_W_PVDD , ARKE_P0V9_OWL_E_PVDD , ARKE_PLL_VDDA15_HBM5_HBM7 , ARKE_PLL_VDDA15_HBM1_HBM3 ,
  ARKE_PLL_VDDA15_HBM4_HBM6 , ARKE_PLL_VDDA15_HBM0_HBM2 , ARKE_PVDD1P5 , ARKE_P1V5_PLL_VDDA_SOC ,
  ARKE_P1V5_PLL_VDDA_OWL , ARKE_LDO_IN_1V2 , ARKE_P1V8 , ARKE_P3V3 ,
  ARKE_P5V , ARKE_P12V_UBC_PWRGD , ARKE_P0V75_AVDD_HCSL , ARKE_4V2 ,
  ARKE_MAX_N_VDDRXTX_SMBALRT_N = 0x31 , ARKE_VDDQC_VDDQL_0246_SMBALRT_N , ARKE_MAX_M_VDDQC_1357_SMBALRT_N , ARKE_OWL_W_SMBALRT_N ,
  ARKE_OWL_E_SMBALRT_N , ARKE_NUWA1_VDD_ALERT_R_N , ARKE_NUWA0_VDD_ALERT_R_N , ARKE_POWER_ON_SEQUENCE_FAIL = 0x50 ,
  ARKE_ASIC_THERMTRIP , ARKE_NUWA1_HBM_CATTRIP , ARKE_NUWA0_HBM_CATTRIP
}
 
enum  READ_FILE_OPTION { READ_FILE_ATTR , READ_FILE_DATA }
 

Functions

struct _cmd_echo_req __attribute__ ((packed))
 
uint8_t check_iana (const uint8_t *iana)
 
uint8_t set_iana (uint8_t *buf, uint8_t buf_len)
 
uint8_t send_event_log_to_bmc (struct pldm_addsel_data msg)
 
uint8_t pldm_oem_handler_query (uint8_t code, void **ret_fn)
 

Variables

uint8_t iana [IANA_LEN]
 
uint8_t first_data
 
uint8_t completion_code
 
uint8_t netfn_lun
 
uint8_t cmd
 
uint8_t ipmi_comp_code
 
uint8_t cmd_code
 
uint32_t data_length
 
uint8_t messages []
 
uint8_t transfer_flag
 
uint16_t offset
 
uint16_t size
 
uint32_t crc32
 
uint8_t read_option
 
uint8_t read_info_length
 
struct pldm_oem_read_file_data_info data
 
struct pldm_oem_read_file_attr_info attr
 
uint8_t read_info []
 
uint8_t event_type
 
uint8_t assert_type
 
uint8_t event_data_1
 
uint8_t event_data_2
 
uint8_t event_data_3
 
uint8_t set_value
 
uint8_t get_value
 

Macro Definition Documentation

◆ EVENT_ASSERTED

#define EVENT_ASSERTED   0x01

◆ EVENT_DEASSERTED

#define EVENT_DEASSERTED   0x00

◆ IANA_LEN

#define IANA_LEN   0x03

◆ OEM_EVENT_LEN

#define OEM_EVENT_LEN   0x05

◆ PLDM_OEM_CMD_ECHO

#define PLDM_OEM_CMD_ECHO   0x00

◆ PLDM_OEM_FORCE_UPDATE_GETTING_CMD

#define PLDM_OEM_FORCE_UPDATE_GETTING_CMD   0x07

◆ PLDM_OEM_FORCE_UPDATE_SETTING_CMD

#define PLDM_OEM_FORCE_UPDATE_SETTING_CMD   0x06

◆ PLDM_OEM_IPMI_BRIDGE

#define PLDM_OEM_IPMI_BRIDGE   0x01

◆ PLDM_OEM_READ_FILE_IO

#define PLDM_OEM_READ_FILE_IO   0x03

◆ PLDM_OEM_SENSOR_POLLING_CMD

#define PLDM_OEM_SENSOR_POLLING_CMD   0x04

◆ PLDM_OEM_WF_READ_SPD_CHUNK

#define PLDM_OEM_WF_READ_SPD_CHUNK   0x05

◆ PLDM_OEM_WRITE_FILE_IO

#define PLDM_OEM_WRITE_FILE_IO   0x02

◆ POWER_CONTROL_LEN

#define POWER_CONTROL_LEN   0x01

Enumeration Type Documentation

◆ arke_event_source

enum arke_event_source
Enumerator
ARKE_HAMSA_VDDHRXTX_PCIE 
ARKE_HAMSA_AVDD_PCIE 
ARKE_OWL_W_TRVDD0P75 
ARKE_OWL_E_TRVDD0P75 
ARKE_OWL_W_TRVDD0P9 
ARKE_OWL_E_TRVDD0P9 
ARKE_MAX_N_VDD 
ARKE_MAX_M_VDD 
ARKE_MAX_S_VDD 
ARKE_HAMSA_VDD 
ARKE_OWL_W_VDD 
ARKE_OWL_E_VDD 
ARKE_NUWA0_VDD 
ARKE_NUWA1_VDD 
ARKE_VDDPHY_HBM1_HBM3_HBM5_HBM7 
ARKE_VPP_HBM1_HBM3_HBM5_HBM7 
ARKE_VDDC_HBM1_HBM3_HBM5_HBM7 
ARKE_VDDQL_HBM1_HBM3_HBM5_HBM7 
ARKE_VDDPHY_HBM0_HBM2_HBM4_HBM6 
ARKE_VPP_HBM0_HBM2_HBM4_HBM6 
ARKE_VDDC_HBM0_HBM2_HBM4_HBM6 
ARKE_VDDQL_HBM0_HBM2_HBM4_HBM6 
ARKE_P1V5_W_RVDD 
ARKE_P1V5_E_RVDD 
ARKE_P0V9_OWL_W_PVDD 
ARKE_P0V9_OWL_E_PVDD 
ARKE_PLL_VDDA15_HBM5_HBM7 
ARKE_PLL_VDDA15_HBM1_HBM3 
ARKE_PLL_VDDA15_HBM4_HBM6 
ARKE_PLL_VDDA15_HBM0_HBM2 
ARKE_PVDD1P5 
ARKE_P1V5_PLL_VDDA_SOC 
ARKE_P1V5_PLL_VDDA_OWL 
ARKE_LDO_IN_1V2 
ARKE_P1V8 
ARKE_P3V3 
ARKE_P5V 
ARKE_P12V_UBC_PWRGD 
ARKE_P0V75_AVDD_HCSL 
ARKE_4V2 
ARKE_MAX_N_VDDRXTX_SMBALRT_N 
ARKE_VDDQC_VDDQL_0246_SMBALRT_N 
ARKE_MAX_M_VDDQC_1357_SMBALRT_N 
ARKE_OWL_W_SMBALRT_N 
ARKE_OWL_E_SMBALRT_N 
ARKE_NUWA1_VDD_ALERT_R_N 
ARKE_NUWA0_VDD_ALERT_R_N 
ARKE_POWER_ON_SEQUENCE_FAIL 
ARKE_ASIC_THERMTRIP 
ARKE_NUWA1_HBM_CATTRIP 
ARKE_NUWA0_HBM_CATTRIP 

◆ cmd_type

enum cmd_type
Enumerator
POST_CODE 
BIOS_VERSION 
POWER_CONTROL 
HTTP_BOOT 
APML_ALERT 
EVENT_LOG 
CRASH_DUMP 
BOOT_ORDER 

◆ iris_event_source

enum iris_event_source
Enumerator
IRIS_HAMSA_VDDHRXTX_PCIE 
IRIS_HAMSA_AVDD_PCIE 
IRIS_OWL_W_TRVDD0P75 
IRIS_OWL_E_TRVDD0P75 
IRIS_OWL_W_TRVDD0P9 
IRIS_OWL_E_TRVDD0P9 
IRIS_MAX_N_VDD 
IRIS_MAX_M_VDD 
IRIS_MAX_S_VDD 
IRIS_HAMSA_VDD 
IRIS_OWL_W_VDD 
IRIS_OWL_E_VDD 
IRIS_MEDHA0_VDD 
IRIS_MEDHA1_VDD 
IRIS_VDDPHY_HBM1_HBM3_HBM5_HBM7 
IRIS_VPP_HBM1_HBM3_HBM5_HBM7 
IRIS_VDDQC_HBM1_HBM3_HBM5_HBM7 
IRIS_VDDQL_HBM1_HBM3_HBM5_HBM7 
IRIS_VDDPHY_HBM0_HBM2_HBM4_HBM6 
IRIS_VPP_HBM0_HBM2_HBM4_HBM6 
IRIS_VDDQC_HBM0_HBM2_HBM4_HBM6 
IRIS_VDDQL_HBM0_HBM2_HBM4_HBM6 
IRIS_P1V5_W_RVDD 
IRIS_P1V5_E_RVDD 
IRIS_P0V9_OWL_W_PVDD 
IRIS_P0V9_OWL_E_PVDD 
IRIS_PLL_VDDA15_HBM5_HBM7 
IRIS_PLL_VDDA15_HBM1_HBM3 
IRIS_PLL_VDDA15_HBM4_HBM6 
IRIS_PLL_VDDA15_HBM0_HBM2 
IRIS_PVDD1P5 
IRIS_P1V5_PLL_VDDA_SOC 
IRIS_P1V5_PLL_VDDA_OWL 
IRIS_LDO_IN_1V2 
IRIS_P1V8 
IRIS_P3V3 
IRIS_P5V 
IRIS_P12V_UBC_PWRGD 
IRIS_P0V75_AVDD_HCSL 
IRIS_4V2 
IRIS_MAX_N_VDDRXTX_SMBALRT_N 
IRIS_VDDQC_VDDQL_0246_SMBALRT_N 
IRIS_MAX_M_VDDQC_1357_SMBALRT_N 
IRIS_OWL_W_SMBALRT_N 
IRIS_OWL_E_SMBALRT_N 
IRIS_MEDHA1_VDD_ALERT_R_N 
IRIS_MEDHA0_VDD_ALERT_R_N 
IRIS_POWER_ON_SEQUENCE_FAIL 
IRIS_ASIC_THERMTRIP 
IRIS_MEDHA1_HBM_CATTRIP 
IRIS_MEDHA0_HBM_CATTRIP 

◆ mtia_event_source

enum mtia_event_source
Enumerator
MTIA_P3V3 
MTIA_P0V85_PVDD 
MTIA_P0V75_PVDD_CH_N 
MTIA_P0V75_MAX_PHY_N 
MTIA_P0V75_PVDD_CH_S 
MTIA_P0V75_MAX_PHY_S 
MTIA_P0V75_TRVDD_ZONEA 
MTIA_P1V8_VPP_HBM0_HBM2_HBM4 
MTIA_P0V75_TRVDD_ZONEB 
MTIA_P0V4_VDDQL_HBM0_HBM2_HBM4 
MTIA_P1V1_VDDC_HBM0_HBM2_HBM4 
MTIA_P0V75_VDDPHY_HBM0_HBM2_HBM4 
MTIA_P0V9_TRVDD_ZONEA 
MTIA_P1V8_VPP_HBM1_HBM3_HBM5 
MTIA_P0V9_TRVDD_ZONEB 
MTIA_P0V4_VDDQL_HBM1_HBM3_HBM5 
MTIA_P1V1_VDDC_HBM1_HBM3_HBM5 
MTIA_P0V75_VDDPHY_HBM1_HBM3_HBM5 
MTIA_P0V8_VDDA_PCIE 
MTIA_P1V2_VDDHTX_PCIE 
MTIA_P12V_UBC1 
MTIA_P12V_UBC2 
MTIA_VR_MAX 
MTIA_PLL_VDDA15_PCIE_MAX_CORE 
MTIA_P0V75_AVDD_HSCL 
MTIA_P0V75_VDDC_CLKOBS 
MTIA_PLL_VDDA15_MAX_CORE_N 
MTIA_PVDD1P5_S 
MTIA_PVDD1P5_N 
MTIA_PVDD0P9_S 
MTIA_PVDD0P9_N 
MTIA_PLL_VDDA15_HBM0_HBM2_HBM4 
MTIA_PLL_VDDA15_HBM1_HBM3_HBM5 
MTIA_P3V3_OSC 
MTIA_P5V 
MTIA_LDO_IN_1V8 
MTIA_LDO_IN_1V2 
MTIA_PLL_VDDA15_MAX_CORE_S 
MTIA_POWER_ON_SEQUENCE_FAIL 
MTIA_FM_ASIC_0_THERMTRIP_N 
MTIA_FM_ATH_PLD_HBM3_CATTRIP_ALARM 
MTIA_VR_FAULT_CAUSE_POWER_DOWN 
MTIA_ATH_GPIO_3 
MTIA_ATH_GPIO_4 

◆ oem_event_type

enum oem_event_type
Enumerator
CPU_THERMAL_TRIP 
HSC_OCP 
P12V_STBY_UV 
PMALERT_ASSERT 
FAST_PROCHOT_ASSERT 
FRB3_TIMER_EXPIRE 
POWER_ON_SEQUENCE_FAIL 
DIMM_PMIC_ERROR 
ADDC_DUMP 
BMC_COMES_OUT_COLD_RESET 
BIOS_FRB2_WDT_EXPIRE 
BIC_POWER_FAIL 
CPU_POWER_FAIL 
BMC_VBOOT_FAIL 
BMC_REBOOT_REQUESTED 
CHASSIS_POWER_ON_BY_NIC_INSERT 
BLADE_POWER_CYCLE_BY_BLADE_BTN 
CHASSIS_POWER_CYCLE_BY_SLED_BTN 
HSC_FAULT 
SYS_THROTTLE 
VR_FAULT 
SYS_MANAGEMENT_ERROR 
POST_COMPLETED 
FAN_ERROR 
HDT_PRSNT_ASSERT 
PLTRST_ASSERT 
APML_ALERT_ASSERT 
CXL1_HB 
CXL2_HB 
POST_STARTED 
POST_ENDED 
PROCHOT_TRIGGERED_BY_SENSOR_UCR 
FRB2_WDT_HARD_RST 
FRB2_WDT_PWR_DOWN 
FRB2_WDT_PWR_CYCLE 
OS_LOAD_WDT_EXPIRED 
OS_LOAD_WDT_HARD_RST 
OS_LOAD_WDT_PWR_DOWN 
OS_LOAD_WDT_PWR_CYCLE 
MTIA_FAULT 
POST_TIMEOUTED 
IRIS_FAULT 
ARKE_FAULT 

◆ POWER_CONTROL_OPTION

enum POWER_CONTROL_OPTION
Enumerator
SLED_CYCLE 
SLOT_12V_CYCLE 
SLOT_DC_CYCLE 
NIC0_POWER_CYCLE 
NIC1_POWER_CYCLE 
NIC2_POWER_CYCLE 
NIC3_POWER_CYCLE 
MAX_POWER_OPTION 

◆ READ_FILE_OPTION

enum READ_FILE_OPTION
Enumerator
READ_FILE_ATTR 
READ_FILE_DATA 

◆ vr_event_source

enum vr_event_source
Enumerator
PVDDCR_CPU0 
PVDDCR_SOC 
PVDDCR_CPU1 
PVDDIO 
PVDD11_S3 
PVDDQ_AB_ASIC1 
P0V85_ASIC1 
PVDDQ_CD_ASIC1 
P0V8_ASIC1 
PVDDQ_AB_ASIC2 
P0V85_ASIC2 
PVDDQ_CD_ASIC2 
P0V8_ASIC2 
P1V5_RETIMER_1 
P0V9_STBY_1 
P3V3_E1S_0 
P3V3_E1S_1 
P12V_E1S_0 
P12V_E1S_1 
PVTT_AB_ASIC1 
PVTT_AB_ASIC2 
PVTT_CD_ASIC1 
PVTT_CD_ASIC2 
PVPP_AB_ASIC1 
PVPP_AB_ASIC2 
PVPP_CD_ASIC1 
PVPP_CD_ASIC2 

Function Documentation

◆ __attribute__()

struct _cmd_echo_req __attribute__ ( (packed)  )

◆ check_iana()

uint8_t check_iana ( const uint8_t *  iana)

◆ pldm_oem_handler_query()

uint8_t pldm_oem_handler_query ( uint8_t  code,
void **  ret_fn 
)

◆ send_event_log_to_bmc()

uint8_t send_event_log_to_bmc ( struct pldm_addsel_data  msg)

◆ set_iana()

uint8_t set_iana ( uint8_t *  buf,
uint8_t  buf_len 
)

Variable Documentation

◆ assert_type

uint8_t assert_type

◆ attr

struct pldm_oem_read_file_attr_info attr

◆ cmd

uint8_t cmd

◆ cmd_code

uint8_t cmd_code

◆ completion_code

uint8_t completion_code

◆ crc32

uint32_t crc32

◆ data

struct pldm_oem_read_file_data_info data

◆ data_length

uint32_t data_length

◆ event_data_1

uint8_t event_data_1

◆ event_data_2

uint8_t event_data_2

◆ event_data_3

uint8_t event_data_3

◆ event_type

uint8_t event_type

◆ first_data

uint8_t first_data

◆ get_value

uint8_t get_value

◆ iana

uint8_t iana

◆ ipmi_comp_code

uint8_t ipmi_comp_code

◆ messages

uint8_t messages[]

◆ netfn_lun

uint8_t netfn_lun

◆ offset

uint16_t offset

◆ read_info

uint8_t read_info

◆ read_info_length

uint8_t read_info_length

◆ read_option

uint8_t read_option

◆ set_value

uint8_t set_value

◆ size

uint16_t size

◆ transfer_flag

uint8_t transfer_flag