plat_fru.h File Reference

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Macros
#define	FRU_CFG_NUM   MAX_FRU_ID
#define	MB_FRU_ADDR   (0xA6 >> 1)
#define	FIO_FRU_ADDR   (0xA4 >> 1)
#define	BB_FRU_ADDR   (0xA4 >> 1)
#define	BPB_FRU_ADDR   (0xA6 >> 1)
#define	SB_FRU_ADDR   (0xA6 >> 1)
#define	PDB_FRU_ADDR   (0xAA >> 1)
#define	PB_FRU_ADDR   (0xA6 >> 1)
#define	FB_FRU_ADDR   (0xA6 >> 1)
#define	I2C_1_MUX_ADDR   (0xE0 >> 1)
#define	I2C_2_MUX_ADDR   (0xE2 >> 1)
#define	I2C_6_MUX_ADDR   (0xE4 >> 1)
#define	I2C_7_MUX_ADDR   (0xE6 >> 1)
#define	PB_MUX_ADDR   (0xE8 >> 1)
#define	SB_MUX_ADDR   (0xE8 >> 1)
#define	MUX_CHANNEL_0   0
#define	MUX_CHANNEL_1   1
#define	MUX_CHANNEL_2   2
#define	MUX_CHANNEL_3   3
#define	MANAGEMENT_BOARD_FRU_EEPROM_OFFSET   0x0000
#define	MANAGEMENT_BOARD_FRU_EEPROM_START_OFFSET   0x0008
#define	MANAGEMENT_BOARD_FRU_EEPROM_BOARD_AREA_SIZE   0x0009
#define	PLAT_EEPROM_OFFSET   0x2000
#define	EEPROM_HMI_VERSION_OFFSET   PLAT_EEPROM_OFFSET
#define	EEPROM_HMI_VERSION_SIZE   8
#define	EEPROM_RPU_ADDR_OFFSET   (EEPROM_HMI_VERSION_OFFSET + EEPROM_HMI_VERSION_SIZE)
#define	EEPROM_RPU_ADDR_VERSION_SIZE   1
#define	EEPROM_UPTIME_OFFSET   (EEPROM_RPU_ADDR_OFFSET + EEPROM_RPU_ADDR_VERSION_SIZE)
#define	EEPROM_UPTIME_SIZE   4
#define	EEPROM_PUMP1_UPTIME_OFFSET   (EEPROM_UPTIME_OFFSET + EEPROM_UPTIME_SIZE)
#define	EEPROM_PUMP1_UPTIME_SIZE   4
#define	EEPROM_PUMP2_UPTIME_OFFSET   (EEPROM_PUMP1_UPTIME_OFFSET + EEPROM_PUMP1_UPTIME_SIZE)
#define	EEPROM_PUMP2_UPTIME_SIZE   4
#define	EEPROM_PUMP3_UPTIME_OFFSET   (EEPROM_PUMP2_UPTIME_OFFSET + EEPROM_PUMP2_UPTIME_SIZE)
#define	EEPROM_PUMP3_UPTIME_SIZE   4

Enumerations
enum	FRU_ID {   MB_FRU_ID = 0x00 , BB_FRU_ID , BPB_FRU_ID , PDB_FRU_ID ,   SB_FRU_ID , PB_1_FRU_ID , PB_2_FRU_ID , PB_3_FRU_ID ,   FB_1_FRU_ID , FB_2_FRU_ID , FB_3_FRU_ID , FB_4_FRU_ID ,   FB_5_FRU_ID , FB_6_FRU_ID , FB_7_FRU_ID , FB_8_FRU_ID ,   FB_9_FRU_ID , FB_10_FRU_ID , FB_11_FRU_ID , FB_12_FRU_ID ,   FB_13_FRU_ID , FB_14_FRU_ID , FIO_FRU_ID , MAX_FRU_ID ,   FIO_FRU_ID = 0x0D , CB_FRU_ID = 0x10 , ACCL_1_FRU_ID = 0x12 , ACCL_2_FRU_ID ,   ACCL_3_FRU_ID , ACCL_4_FRU_ID , ACCL_5_FRU_ID , ACCL_6_FRU_ID ,   ACCL_7_FRU_ID , ACCL_8_FRU_ID , ACCL_9_FRU_ID , ACCL_10_FRU_ID ,   ACCL_11_FRU_ID , ACCL_12_FRU_ID , ACCL_1_CH1_FREYA_FRU_ID = 0x1E , ACCL_1_CH2_FREYA_FRU_ID ,   ACCL_2_CH1_FREYA_FRU_ID , ACCL_2_CH2_FREYA_FRU_ID , ACCL_3_CH1_FREYA_FRU_ID , ACCL_3_CH2_FREYA_FRU_ID ,   ACCL_4_CH1_FREYA_FRU_ID , ACCL_4_CH2_FREYA_FRU_ID , ACCL_5_CH1_FREYA_FRU_ID , ACCL_5_CH2_FREYA_FRU_ID ,   ACCL_6_CH1_FREYA_FRU_ID , ACCL_6_CH2_FREYA_FRU_ID , ACCL_7_CH1_FREYA_FRU_ID , ACCL_7_CH2_FREYA_FRU_ID ,   ACCL_8_CH1_FREYA_FRU_ID , ACCL_8_CH2_FREYA_FRU_ID , ACCL_9_CH1_FREYA_FRU_ID , ACCL_9_CH2_FREYA_FRU_ID ,   ACCL_10_CH1_FREYA_FRU_ID , ACCL_10_CH2_FREYA_FRU_ID , ACCL_11_CH1_FREYA_FRU_ID , ACCL_11_CH2_FREYA_FRU_ID ,   ACCL_12_CH1_FREYA_FRU_ID , ACCL_12_CH2_FREYA_FRU_ID , MAX_FRU_ID , MC_FRU_ID = 0x11 ,   CXL_FRU_ID1 = 0x1E , CXL_FRU_ID2 , CXL_FRU_ID3 , CXL_FRU_ID4 ,   MC_E1S_4_FRU_ID , MC_E1S_3_FRU_ID , MC_E1S_2_FRU_ID , MC_E1S_1_FRU_ID ,   CXL_FRU_ID5 , CXL_FRU_ID6 , CXL_FRU_ID7 , CXL_FRU_ID8 ,   SYS_DEBUG_ID , MAX_FRU_ID , LOG_EEPROM_ID = 0x00 , MAX_FRU_ID ,   VF_FRU_ID , MAX_FRU_ID , NF_FRU_ID = 0 , MAX_FRU_ID ,   RF_FRU_ID , MAX_FRU_ID }

Functions
bool	plat_eeprom_write (uint32_t offset, uint8_t *data, uint16_t data_len)
bool	plat_eeprom_read (uint32_t offset, uint8_t *data, uint16_t data_len)

Macro Definition Documentation

BB_FRU_ADDR

#define BB_FRU_ADDR   (0xA4 >> 1)

BPB_FRU_ADDR

#define BPB_FRU_ADDR   (0xA6 >> 1)

EEPROM_HMI_VERSION_OFFSET

#define EEPROM_HMI_VERSION_OFFSET   PLAT_EEPROM_OFFSET

EEPROM_HMI_VERSION_SIZE

#define EEPROM_HMI_VERSION_SIZE   8

EEPROM_PUMP1_UPTIME_OFFSET

#define EEPROM_PUMP1_UPTIME_OFFSET   (EEPROM_UPTIME_OFFSET + EEPROM_UPTIME_SIZE)

EEPROM_PUMP1_UPTIME_SIZE

#define EEPROM_PUMP1_UPTIME_SIZE   4

EEPROM_PUMP2_UPTIME_OFFSET

#define EEPROM_PUMP2_UPTIME_OFFSET   (EEPROM_PUMP1_UPTIME_OFFSET + EEPROM_PUMP1_UPTIME_SIZE)

EEPROM_PUMP2_UPTIME_SIZE

#define EEPROM_PUMP2_UPTIME_SIZE   4

EEPROM_PUMP3_UPTIME_OFFSET

#define EEPROM_PUMP3_UPTIME_OFFSET   (EEPROM_PUMP2_UPTIME_OFFSET + EEPROM_PUMP2_UPTIME_SIZE)

EEPROM_PUMP3_UPTIME_SIZE

#define EEPROM_PUMP3_UPTIME_SIZE   4

EEPROM_RPU_ADDR_OFFSET

#define EEPROM_RPU_ADDR_OFFSET   (EEPROM_HMI_VERSION_OFFSET + EEPROM_HMI_VERSION_SIZE)

EEPROM_RPU_ADDR_VERSION_SIZE

#define EEPROM_RPU_ADDR_VERSION_SIZE   1

EEPROM_UPTIME_OFFSET

#define EEPROM_UPTIME_OFFSET   (EEPROM_RPU_ADDR_OFFSET + EEPROM_RPU_ADDR_VERSION_SIZE)

EEPROM_UPTIME_SIZE

#define EEPROM_UPTIME_SIZE   4

FB_FRU_ADDR

#define FB_FRU_ADDR   (0xA6 >> 1)

FIO_FRU_ADDR

#define FIO_FRU_ADDR   (0xA4 >> 1)

FRU_CFG_NUM

#define FRU_CFG_NUM   MAX_FRU_ID

I2C_1_MUX_ADDR

#define I2C_1_MUX_ADDR   (0xE0 >> 1)

I2C_2_MUX_ADDR

#define I2C_2_MUX_ADDR   (0xE2 >> 1)

I2C_6_MUX_ADDR

#define I2C_6_MUX_ADDR   (0xE4 >> 1)

I2C_7_MUX_ADDR

#define I2C_7_MUX_ADDR   (0xE6 >> 1)

MANAGEMENT_BOARD_FRU_EEPROM_BOARD_AREA_SIZE

#define MANAGEMENT_BOARD_FRU_EEPROM_BOARD_AREA_SIZE   0x0009

MANAGEMENT_BOARD_FRU_EEPROM_OFFSET

#define MANAGEMENT_BOARD_FRU_EEPROM_OFFSET   0x0000

MANAGEMENT_BOARD_FRU_EEPROM_START_OFFSET

#define MANAGEMENT_BOARD_FRU_EEPROM_START_OFFSET   0x0008

MB_FRU_ADDR

#define MB_FRU_ADDR   (0xA6 >> 1)

MUX_CHANNEL_0

#define MUX_CHANNEL_0   0

MUX_CHANNEL_1

#define MUX_CHANNEL_1   1

MUX_CHANNEL_2

#define MUX_CHANNEL_2   2

MUX_CHANNEL_3

#define MUX_CHANNEL_3   3

PB_FRU_ADDR

#define PB_FRU_ADDR   (0xA6 >> 1)

PB_MUX_ADDR

#define PB_MUX_ADDR   (0xE8 >> 1)

PDB_FRU_ADDR

#define PDB_FRU_ADDR   (0xAA >> 1)

PLAT_EEPROM_OFFSET

#define PLAT_EEPROM_OFFSET   0x2000

SB_FRU_ADDR

#define SB_FRU_ADDR   (0xA6 >> 1)

SB_MUX_ADDR

#define SB_MUX_ADDR   (0xE8 >> 1)

Enumeration Type Documentation

FRU_ID

enum FRU_ID

Enumerator
MB_FRU_ID
BB_FRU_ID
BPB_FRU_ID
PDB_FRU_ID
SB_FRU_ID
PB_1_FRU_ID
PB_2_FRU_ID
PB_3_FRU_ID
FB_1_FRU_ID
FB_2_FRU_ID
FB_3_FRU_ID
FB_4_FRU_ID
FB_5_FRU_ID
FB_6_FRU_ID
FB_7_FRU_ID
FB_8_FRU_ID
FB_9_FRU_ID
FB_10_FRU_ID
FB_11_FRU_ID
FB_12_FRU_ID
FB_13_FRU_ID
FB_14_FRU_ID
FIO_FRU_ID
MAX_FRU_ID
FIO_FRU_ID
CB_FRU_ID
ACCL_1_FRU_ID
ACCL_2_FRU_ID
ACCL_3_FRU_ID
ACCL_4_FRU_ID
ACCL_5_FRU_ID
ACCL_6_FRU_ID
ACCL_7_FRU_ID
ACCL_8_FRU_ID
ACCL_9_FRU_ID
ACCL_10_FRU_ID
ACCL_11_FRU_ID
ACCL_12_FRU_ID
ACCL_1_CH1_FREYA_FRU_ID
ACCL_1_CH2_FREYA_FRU_ID
ACCL_2_CH1_FREYA_FRU_ID
ACCL_2_CH2_FREYA_FRU_ID
ACCL_3_CH1_FREYA_FRU_ID
ACCL_3_CH2_FREYA_FRU_ID
ACCL_4_CH1_FREYA_FRU_ID
ACCL_4_CH2_FREYA_FRU_ID
ACCL_5_CH1_FREYA_FRU_ID
ACCL_5_CH2_FREYA_FRU_ID
ACCL_6_CH1_FREYA_FRU_ID
ACCL_6_CH2_FREYA_FRU_ID
ACCL_7_CH1_FREYA_FRU_ID
ACCL_7_CH2_FREYA_FRU_ID
ACCL_8_CH1_FREYA_FRU_ID
ACCL_8_CH2_FREYA_FRU_ID
ACCL_9_CH1_FREYA_FRU_ID
ACCL_9_CH2_FREYA_FRU_ID
ACCL_10_CH1_FREYA_FRU_ID
ACCL_10_CH2_FREYA_FRU_ID
ACCL_11_CH1_FREYA_FRU_ID
ACCL_11_CH2_FREYA_FRU_ID
ACCL_12_CH1_FREYA_FRU_ID
ACCL_12_CH2_FREYA_FRU_ID
MAX_FRU_ID
MC_FRU_ID
CXL_FRU_ID1
CXL_FRU_ID2
CXL_FRU_ID3
CXL_FRU_ID4
MC_E1S_4_FRU_ID
MC_E1S_3_FRU_ID
MC_E1S_2_FRU_ID
MC_E1S_1_FRU_ID
CXL_FRU_ID5
CXL_FRU_ID6
CXL_FRU_ID7
CXL_FRU_ID8
SYS_DEBUG_ID
MAX_FRU_ID
LOG_EEPROM_ID
MAX_FRU_ID
VF_FRU_ID
MAX_FRU_ID
NF_FRU_ID
MAX_FRU_ID
RF_FRU_ID
MAX_FRU_ID

Function Documentation

plat_eeprom_read()

bool plat_eeprom_read	(	uint32_t	offset,
		uint8_t *	data,
		uint16_t	data_len
	)

plat_eeprom_write()

bool plat_eeprom_write	(	uint32_t	offset,
		uint8_t *	data,
		uint16_t	data_len
	)