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Classes
struct	_aegis_cpld_info_

Macros
#define	POLLING_CPLD_STACK_SIZE 1024

#define	POWER_AND_RESET_BUTTON_REG 0x00

#define	VR_AND_CLK_ENABLE_PIN_READING_REG 0x01

#define	VR_ENABLE_PIN_READING_1_REG 0x02

#define	VR_ENABLE_PIN_READING_2_REG 0x03

#define	VR_ENABLE_PIN_READING_3_REG 0x04

#define	VR_ENABLE_PIN_READING_4_REG 0x05

#define	MB_POWER_GOOD_AND_PERST_PIN_READING_REG 0x06

#define	VR_POWER_GOOD_PIN_READING_1_REG 0x07

#define	VR_POWER_GOOD_PIN_READING_2_REG 0x08

#define	VR_POWER_GOOD_PIN_READING_3_REG 0x09

#define	VR_POWER_GOOD_PIN_READING_4_REG 0x0A

#define	VR_POWER_GOOD_PIN_READING_5_REG 0x0B

#define	RSVD_1_REG 0x0C

#define	VR_POWER_FAULT_1_REG 0x0D

#define	VR_POWER_FAULT_2_REG 0x0E

#define	VR_POWER_FAULT_3_REG 0x0F

#define	VR_POWER_FAULT_4_REG 0x10

#define	VR_POWER_FAULT_5_REG 0x11

#define	RSVD_2_REG 0x12

#define	RSVD_3_REG 0x13

#define	OSFP_PRSNT_PIN_READING_1_REG 0x14

#define	OSFP_PRSNT_PIN_READING_2_REG 0x15

#define	OSFP_POWER_ENABLE_PIN_READING_1_REG 0x16

#define	OSFP_POWER_ENABLE_PIN_READING_2_REG 0x17

#define	OSFP_POWER_ENABLE_PIN_READING_3_REG 0x18

#define	OSFP_POWER_ENABLE_PIN_READING_4_REG 0x19

#define	BOARD_TYPE_REG 0x1A

#define	BOARD_REV_ID_REG 0x1B

#define	VR_VENDOR_TYPE_REG 0x1C

#define	OWL_JTAG_SEL_MUX_REG 0x1D

#define	ATH_JTAG_SEL_MUX_REG 0x1E

#define	OWL_UART_SEL_MUX_REG 0x1F

#define	AEGIS_JTAG_SWITCH_REG 0x20

#define	ATH_BOOT_SOURCE_REG 0x21

#define	S_OWL_BOOT_SOURCE_REG 0x22

#define	N_OWL_BOOT_SOURCE_REG 0x23

#define	VR_SMBUS_ALERT_1_REG 0x24

#define	VR_SMBUS_ALERT_2_REG 0x25

#define	RSVD_4_REG 0x26

#define	ASIC_OC_WARN_REG 0x27

#define	SYSTEM_ALERT_FAULT_REG 0x28

#define	VR_HOT_FAULT_1_REG 0x29

#define	VR_HOT_FAULT_2_REG 0x2A

#define	TEMPERATURE_IC_OVERT_FAULT_REG 0x2B

#define	VR_POWER_INPUT_FAULT_1_REG 0x2C

#define	VR_POWER_INPUT_FAULT_2_REG 0x2D

#define	LEAK_DETCTION_REG 0x2E

#define	RESET_PIN_TO_ICS_STATUS_REG 0x2F

#define	CRD_STATUS_REG 0x30

#define	CMN_STATUS_REG 0x31

#define	RSVD_GPIO_STATUS_REG 0x32

#define	UART_IC_STATUS_REG 0x33

#define	UBC_MODULE_OC_WARNING_REG 0x34

#define	CPLD_EEPROM_STATUS_REG 0x35

#define	MTIA_N_OWL_TEST_PIN_STATUS_REG 0x36

#define	MTIA_S_OWL_TEST_PIN_STATUS_REG 0x37

#define	MTIA_ATH_TEST_PIN_STATUS_REG 0x38

#define	MTIA_VQPS_TO_EFUSE_PROGRAMMING_REG 0x39

#define	BUFFER_100M_CLK_LOSE_OF_INPUT_SIGNAL_REG 0x3A

#define	MTIA_QSPI_BOOT_DISABLE_REG 0x3B

#define	ATH_RSVD_GPIO_REG 0x3C

Typedefs
typedef struct _aegis_cpld_info_	aegis_cpld_info

Functions
void	check_ubc_delayed (struct k_timer *timer)

void	set_dc_status_changing_status (bool status)

void	init_cpld_polling (void)

Macro Definition Documentation

◆ AEGIS_JTAG_SWITCH_REG

#define AEGIS_JTAG_SWITCH_REG 0x20

◆ ASIC_OC_WARN_REG

#define ASIC_OC_WARN_REG 0x27

◆ ATH_BOOT_SOURCE_REG

#define ATH_BOOT_SOURCE_REG 0x21

◆ ATH_JTAG_SEL_MUX_REG

#define ATH_JTAG_SEL_MUX_REG 0x1E

◆ ATH_RSVD_GPIO_REG

#define ATH_RSVD_GPIO_REG 0x3C

◆ BOARD_REV_ID_REG

#define BOARD_REV_ID_REG 0x1B

◆ BOARD_TYPE_REG

#define BOARD_TYPE_REG 0x1A

◆ BUFFER_100M_CLK_LOSE_OF_INPUT_SIGNAL_REG

#define BUFFER_100M_CLK_LOSE_OF_INPUT_SIGNAL_REG 0x3A

◆ CMN_STATUS_REG

#define CMN_STATUS_REG 0x31

◆ CPLD_EEPROM_STATUS_REG

#define CPLD_EEPROM_STATUS_REG 0x35

◆ CRD_STATUS_REG

#define CRD_STATUS_REG 0x30

◆ LEAK_DETCTION_REG

#define LEAK_DETCTION_REG 0x2E

◆ MB_POWER_GOOD_AND_PERST_PIN_READING_REG

#define MB_POWER_GOOD_AND_PERST_PIN_READING_REG 0x06

◆ MTIA_ATH_TEST_PIN_STATUS_REG

#define MTIA_ATH_TEST_PIN_STATUS_REG 0x38

◆ MTIA_N_OWL_TEST_PIN_STATUS_REG

#define MTIA_N_OWL_TEST_PIN_STATUS_REG 0x36

◆ MTIA_QSPI_BOOT_DISABLE_REG

#define MTIA_QSPI_BOOT_DISABLE_REG 0x3B

◆ MTIA_S_OWL_TEST_PIN_STATUS_REG

#define MTIA_S_OWL_TEST_PIN_STATUS_REG 0x37

◆ MTIA_VQPS_TO_EFUSE_PROGRAMMING_REG

#define MTIA_VQPS_TO_EFUSE_PROGRAMMING_REG 0x39

◆ N_OWL_BOOT_SOURCE_REG

#define N_OWL_BOOT_SOURCE_REG 0x23

◆ OSFP_POWER_ENABLE_PIN_READING_1_REG

#define OSFP_POWER_ENABLE_PIN_READING_1_REG 0x16

◆ OSFP_POWER_ENABLE_PIN_READING_2_REG

#define OSFP_POWER_ENABLE_PIN_READING_2_REG 0x17

◆ OSFP_POWER_ENABLE_PIN_READING_3_REG

#define OSFP_POWER_ENABLE_PIN_READING_3_REG 0x18

◆ OSFP_POWER_ENABLE_PIN_READING_4_REG

#define OSFP_POWER_ENABLE_PIN_READING_4_REG 0x19

◆ OSFP_PRSNT_PIN_READING_1_REG

#define OSFP_PRSNT_PIN_READING_1_REG 0x14

◆ OSFP_PRSNT_PIN_READING_2_REG

#define OSFP_PRSNT_PIN_READING_2_REG 0x15

◆ OWL_JTAG_SEL_MUX_REG

#define OWL_JTAG_SEL_MUX_REG 0x1D

◆ OWL_UART_SEL_MUX_REG

#define OWL_UART_SEL_MUX_REG 0x1F

◆ POLLING_CPLD_STACK_SIZE

#define POLLING_CPLD_STACK_SIZE 1024

◆ POWER_AND_RESET_BUTTON_REG

#define POWER_AND_RESET_BUTTON_REG 0x00

◆ RESET_PIN_TO_ICS_STATUS_REG

#define RESET_PIN_TO_ICS_STATUS_REG 0x2F

◆ RSVD_1_REG

#define RSVD_1_REG 0x0C

◆ RSVD_2_REG

#define RSVD_2_REG 0x12

◆ RSVD_3_REG

#define RSVD_3_REG 0x13

◆ RSVD_4_REG

#define RSVD_4_REG 0x26

◆ RSVD_GPIO_STATUS_REG

#define RSVD_GPIO_STATUS_REG 0x32

◆ S_OWL_BOOT_SOURCE_REG

#define S_OWL_BOOT_SOURCE_REG 0x22

◆ SYSTEM_ALERT_FAULT_REG

#define SYSTEM_ALERT_FAULT_REG 0x28

◆ TEMPERATURE_IC_OVERT_FAULT_REG

#define TEMPERATURE_IC_OVERT_FAULT_REG 0x2B

◆ UART_IC_STATUS_REG

#define UART_IC_STATUS_REG 0x33

◆ UBC_MODULE_OC_WARNING_REG

#define UBC_MODULE_OC_WARNING_REG 0x34

◆ VR_AND_CLK_ENABLE_PIN_READING_REG

#define VR_AND_CLK_ENABLE_PIN_READING_REG 0x01

◆ VR_ENABLE_PIN_READING_1_REG

#define VR_ENABLE_PIN_READING_1_REG 0x02

◆ VR_ENABLE_PIN_READING_2_REG

#define VR_ENABLE_PIN_READING_2_REG 0x03

◆ VR_ENABLE_PIN_READING_3_REG

#define VR_ENABLE_PIN_READING_3_REG 0x04

◆ VR_ENABLE_PIN_READING_4_REG

#define VR_ENABLE_PIN_READING_4_REG 0x05

◆ VR_HOT_FAULT_1_REG

#define VR_HOT_FAULT_1_REG 0x29

◆ VR_HOT_FAULT_2_REG

#define VR_HOT_FAULT_2_REG 0x2A

◆ VR_POWER_FAULT_1_REG

#define VR_POWER_FAULT_1_REG 0x0D

◆ VR_POWER_FAULT_2_REG

#define VR_POWER_FAULT_2_REG 0x0E

◆ VR_POWER_FAULT_3_REG

#define VR_POWER_FAULT_3_REG 0x0F

◆ VR_POWER_FAULT_4_REG

#define VR_POWER_FAULT_4_REG 0x10

◆ VR_POWER_FAULT_5_REG

#define VR_POWER_FAULT_5_REG 0x11

◆ VR_POWER_GOOD_PIN_READING_1_REG

#define VR_POWER_GOOD_PIN_READING_1_REG 0x07

◆ VR_POWER_GOOD_PIN_READING_2_REG

#define VR_POWER_GOOD_PIN_READING_2_REG 0x08

◆ VR_POWER_GOOD_PIN_READING_3_REG

#define VR_POWER_GOOD_PIN_READING_3_REG 0x09

◆ VR_POWER_GOOD_PIN_READING_4_REG

#define VR_POWER_GOOD_PIN_READING_4_REG 0x0A

◆ VR_POWER_GOOD_PIN_READING_5_REG

#define VR_POWER_GOOD_PIN_READING_5_REG 0x0B

◆ VR_POWER_INPUT_FAULT_1_REG

#define VR_POWER_INPUT_FAULT_1_REG 0x2C

◆ VR_POWER_INPUT_FAULT_2_REG

#define VR_POWER_INPUT_FAULT_2_REG 0x2D

◆ VR_SMBUS_ALERT_1_REG

#define VR_SMBUS_ALERT_1_REG 0x24

◆ VR_SMBUS_ALERT_2_REG

#define VR_SMBUS_ALERT_2_REG 0x25

◆ VR_VENDOR_TYPE_REG

#define VR_VENDOR_TYPE_REG 0x1C

Typedef Documentation

◆ aegis_cpld_info

typedef struct _aegis_cpld_info_ aegis_cpld_info

Function Documentation

◆ check_ubc_delayed()

void check_ubc_delayed ( struct k_timer * timer )

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◆ init_cpld_polling()

void init_cpld_polling ( void )