22#define CXL_IOEXP_U14_ADDR (0x42 >> 1)
23#define CXL_IOEXP_U15_ADDR (0x44 >> 1)
24#define CXL_IOEXP_U16_ADDR (0x46 >> 1)
25#define CXL_IOEXP_U17_ADDR (0x48 >> 1)
26#define CXL_IOEXP_MUX_CHANNEL 0x10
27#define CXL_IOEXP_MB_RESET_BIT BIT(0)
28#define CXL_IOEXP_DEV_RESET_BIT BIT(2)
29#define CXL_IOEXP_ASIC_PERESET_BIT BIT(6)
30#define CXL_IOEXP_CONTROLLER_PWRGD_VAL 0x7F
31#define CXL_IOEXP_DIMM_PWRGD_VAL 0x07
32#define CXL_NOT_ALL_POWER_GOOD 0
33#define CXL_ALL_POWER_GOOD 1
35#define CXL_CONTROLLER_MUX_CHANNEL 0x01
36#define CXL_DRIVE_READY_DELAY_MS 1000
37#define CXL_DEBUG_SEL_DELAY_MS 500
38#define CXL_POWER_GOOD_DELAY_MS 12
Definition: plat_isr.h:47
bool is_mb_reset
Definition: plat_isr.h:52
struct k_work_delayable device_reset_work
Definition: plat_isr.h:54
struct k_work_delayable perst_add_sel_work
Definition: plat_isr.h:56
bool is_init
Definition: plat_isr.h:48
uint8_t cxl_channel
Definition: plat_isr.h:50
bool is_device_reset
Definition: plat_isr.h:51
uint8_t cxl_card_id
Definition: plat_isr.h:49
struct k_work_delayable set_eid_work
Definition: plat_isr.h:55
bool is_pe_reset
Definition: plat_isr.h:53