plat_cpld.h File Reference

#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <zephyr.h>

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Classes
struct	_cpld_info_
struct	cpld_pin_map_t

Macros
#define	RESET   0x00
#define	CPLD_OFFSET_BOARD_REV_ID   0x14
#define	CPLD_OFFSET_VR_VENDER_TYPE   0x15
#define	CPLD_OFFSET_POWER_CLAMP   0x25
#define	CPLD_OFFSET_USERCODE   0x32
#define	CPLD_OFFSET_MMC_PWR_EN   0x38
#define	CPLD_OFFSET_ASIC_BOARD_ID   0x3C
#define	CPLD_OFFSET_ADC_IDX   0xA0
#define	CPLD_OFFSET_ASIC_RST_DELAY   0xA4
#define	CPLD_OFFSET_MODULE_PG_DELAY   0xA5
#define	VR_AND_CLK_EN   0x3E
#define	VR_1_EN   0x3F
#define	VR_2_EN   0x40
#define	VR_3_EN   0x41
#define	VR_4_EN   0x42
#define	CPLD_HAMSA_PCIE0_PERST_DELAY_REG   0x9D
#define	CPLD_HAMSA_PCIE1_PERST_DELAY_REG   0xB3
#define	CPLD_HAMSA_PCIE2_PERST_DELAY_REG   0xB4
#define	CPLD_HAMSA_PCIE3_PERST_DELAY_REG   0xB5
#define	CPLD_POWER_INFO_0_REG   0xB6
#define	CPLD_POWER_INFO_1_REG   0xB7
#define	PREST_DELAY_REG   0x9D
#define	VR_SMBUS_ALERT_EVENT_LOG_REG   0x26
#define	HAMSA_MFIO_REG   0x17
#define	VR_AND_CLK_EN_PIN_CTRL   0xA1
#define	ASIC_VR_HOT_SWITCH   0x12
#define	ASIC_JTAG_MUX_SEL   0x39
#define	ASIC_VQPS   0x13
#define	VR_PWRGD_PIN_READING_1_REG   0x07
#define	VR_PWRGD_PIN_READING_2_REG   0x08
#define	VR_PWRGD_PIN_READING_3_REG   0x09
#define	VR_PWRGD_PIN_READING_4_REG   0x0A
#define	VR_PWRGD_PIN_READING_5_REG   0x0B
#define	VR_PWRGD_PIN_READING_6_REG   0x0C
#define	VR_CLK_ENABLE_PIN_CTRL_REG   0xA1
#define	VR_1STEP_FUNC_EN_REG   0xA9
#define	CPLD_ADDR   (0x4C >> 1)
#define	I2C_BUS_CPLD   I2C_BUS11

Typedefs
typedef struct _cpld_info_	cpld_info

Functions
void	check_ubc_delayed (struct k_work *work)
bool	is_ubc_enabled_delayed_enabled (void)
bool	plat_read_cpld (uint8_t offset, uint8_t *data, uint8_t len)
bool	plat_write_cpld (uint8_t offset, uint8_t *data)
void	init_cpld_polling (void)
void	check_cpld_polling_alert_status (void)
void	check_ubc_delayed_timer_handler (struct k_timer *timer)
bool	set_cpld_bit (uint8_t cpld_offset, uint8_t bit, uint8_t value)
void	give_all_vr_pm_alert_sem ()
void	get_cpld_polling_power_info (int *reading)

Macro Definition Documentation

ASIC_JTAG_MUX_SEL

#define ASIC_JTAG_MUX_SEL   0x39

ASIC_VQPS

#define ASIC_VQPS   0x13

ASIC_VR_HOT_SWITCH

#define ASIC_VR_HOT_SWITCH   0x12

CPLD_ADDR

#define CPLD_ADDR   (0x4C >> 1)

CPLD_HAMSA_PCIE0_PERST_DELAY_REG

#define CPLD_HAMSA_PCIE0_PERST_DELAY_REG   0x9D

CPLD_HAMSA_PCIE1_PERST_DELAY_REG

#define CPLD_HAMSA_PCIE1_PERST_DELAY_REG   0xB3

CPLD_HAMSA_PCIE2_PERST_DELAY_REG

#define CPLD_HAMSA_PCIE2_PERST_DELAY_REG   0xB4

CPLD_HAMSA_PCIE3_PERST_DELAY_REG

#define CPLD_HAMSA_PCIE3_PERST_DELAY_REG   0xB5

CPLD_OFFSET_ADC_IDX

#define CPLD_OFFSET_ADC_IDX   0xA0

CPLD_OFFSET_ASIC_BOARD_ID

#define CPLD_OFFSET_ASIC_BOARD_ID   0x3C

CPLD_OFFSET_ASIC_RST_DELAY

#define CPLD_OFFSET_ASIC_RST_DELAY   0xA4

CPLD_OFFSET_BOARD_REV_ID

#define CPLD_OFFSET_BOARD_REV_ID   0x14

CPLD_OFFSET_MMC_PWR_EN

#define CPLD_OFFSET_MMC_PWR_EN   0x38

CPLD_OFFSET_MODULE_PG_DELAY

#define CPLD_OFFSET_MODULE_PG_DELAY   0xA5

CPLD_OFFSET_POWER_CLAMP

#define CPLD_OFFSET_POWER_CLAMP   0x25

CPLD_OFFSET_USERCODE

#define CPLD_OFFSET_USERCODE   0x32

CPLD_OFFSET_VR_VENDER_TYPE

#define CPLD_OFFSET_VR_VENDER_TYPE   0x15

CPLD_POWER_INFO_0_REG

#define CPLD_POWER_INFO_0_REG   0xB6

CPLD_POWER_INFO_1_REG

#define CPLD_POWER_INFO_1_REG   0xB7

HAMSA_MFIO_REG

#define HAMSA_MFIO_REG   0x17

I2C_BUS_CPLD

#define I2C_BUS_CPLD   I2C_BUS11

PREST_DELAY_REG

#define PREST_DELAY_REG   0x9D

RESET

#define RESET   0x00

VR_1_EN

#define VR_1_EN   0x3F

VR_1STEP_FUNC_EN_REG

#define VR_1STEP_FUNC_EN_REG   0xA9

VR_2_EN

#define VR_2_EN   0x40

VR_3_EN

#define VR_3_EN   0x41

VR_4_EN

#define VR_4_EN   0x42

VR_AND_CLK_EN

#define VR_AND_CLK_EN   0x3E

VR_AND_CLK_EN_PIN_CTRL

#define VR_AND_CLK_EN_PIN_CTRL   0xA1

VR_CLK_ENABLE_PIN_CTRL_REG

#define VR_CLK_ENABLE_PIN_CTRL_REG   0xA1

VR_PWRGD_PIN_READING_1_REG

#define VR_PWRGD_PIN_READING_1_REG   0x07

VR_PWRGD_PIN_READING_2_REG

#define VR_PWRGD_PIN_READING_2_REG   0x08

VR_PWRGD_PIN_READING_3_REG

#define VR_PWRGD_PIN_READING_3_REG   0x09

VR_PWRGD_PIN_READING_4_REG

#define VR_PWRGD_PIN_READING_4_REG   0x0A

VR_PWRGD_PIN_READING_5_REG

#define VR_PWRGD_PIN_READING_5_REG   0x0B

VR_PWRGD_PIN_READING_6_REG

#define VR_PWRGD_PIN_READING_6_REG   0x0C

VR_SMBUS_ALERT_EVENT_LOG_REG

#define VR_SMBUS_ALERT_EVENT_LOG_REG   0x26

Typedef Documentation

cpld_info

typedef struct _cpld_info_ cpld_info

Function Documentation

check_cpld_polling_alert_status()

void check_cpld_polling_alert_status

(

void

)

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check_ubc_delayed()

void check_ubc_delayed

(

struct k_work *

work

)

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check_ubc_delayed_timer_handler()

void check_ubc_delayed_timer_handler

(

struct k_timer *

timer

)

get_cpld_polling_power_info()

void get_cpld_polling_power_info

(

int *

reading

)

give_all_vr_pm_alert_sem()

void give_all_vr_pm_alert_sem

(

)

init_cpld_polling()

void init_cpld_polling

(

void

)

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is_ubc_enabled_delayed_enabled()

bool is_ubc_enabled_delayed_enabled

(

void

)

plat_read_cpld()

bool plat_read_cpld	(	uint8_t	offset,
		uint8_t *	data,
		uint8_t	len
	)

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plat_write_cpld()

bool plat_write_cpld	(	uint8_t	offset,
		uint8_t *	data
	)

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set_cpld_bit()

bool set_cpld_bit	(	uint8_t	cpld_offset,
		uint8_t	bit,
		uint8_t	value
	)

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