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#define | ADDR_UNKNOWN (0xFF >> 1) |
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#define | UBC1_ADDR (0x28 >> 1) |
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#define | UBC2_ADDR (0x34 >> 1) |
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#define | TOP_INLET_TEMP_ADDR (0x92 >> 1) |
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#define | TOP_OUTLET_TEMP_ADDR (0x9E >> 1) |
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#define | BOT_INLET_TEMP_ADDR (0x94 >> 1) |
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#define | BOT_OUTLET_TEMP_ADDR (0X96 >> 1) |
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#define | ASIC_DIE_ATH_SENSOR_0_TEMP_TMP432_ADDR (0X98 >> 1) |
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#define | ASIC_DIE_ATH_SENSOR_1_TEMP_TMP432_ADDR (0X9A >> 1) |
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#define | ASIC_DIE_N_OWL_TEMP_TMP432_ADDR (0X98 >> 1) |
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#define | ASIC_DIE_S_OWL_TEMP_TMP432_ADDR (0X9A >> 1) |
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#define | ASIC_DIE_ATH_SENSOR_0_TEMP_EMC1413_ADDR (0XB8 >> 1) |
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#define | ASIC_DIE_ATH_SENSOR_1_TEMP_EMC1413_ADDR (0XB8 >> 1) |
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#define | ON_DIE_3_TEMP_EMC1413_ADDR (0X38 >> 1) |
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#define | ASIC_DIE_S_OWL_TEMP_EMC1413_ADDR (0X38 >> 1) |
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#define | VR_P3V3_MP2971_ADDR (0xF6 >> 1) |
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#define | VR_P3V3_MP2971_FAB3_ADDR (0xD6 >> 1) |
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#define | VR_P3V3_ISL69260_ADDR (0xC0 >> 1) |
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#define | VR_ASIC_P0V85_PVDD_MP2891_ADDR (0x4C >> 1) |
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#define | VR_ASIC_P0V85_PVDD_RAA228238_ADDR (0xE4 >> 1) |
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#define | VR_ASIC_P0V75_PVDD_CH_N_MP2971_ADDR (0xE0 >> 1) |
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#define | VR_ASIC_P0V75_PVDD_CH_N_ISL69260_ADDR (0xC0 >> 1) |
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#define | VR_ASIC_P0V75_MAX_PHY_N_MP2971_ADDR (0xE0 >> 1) |
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#define | VR_ASIC_P0V75_MAX_PHY_N_ISL69260_ADDR (0xC0 >> 1) |
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#define | VR_ASIC_P0V75_PVDD_CH_S_MP2971_ADDR (0xE2 >> 1) |
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#define | VR_ASIC_P0V75_PVDD_CH_S_ISL69260_ADDR (0xC2 >> 1) |
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#define | VR_ASIC_P0V75_MAX_PHY_S_MP2971_ADDR (0xE2 >> 1) |
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#define | VR_ASIC_P0V75_MAX_PHY_S_ISL69260_ADDR (0xC2 >> 1) |
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#define | VR_ASIC_P0V75_TRVDD_ZONEA_MP2971_ADDR (0xE6 >> 1) |
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#define | VR_ASIC_P0V75_TRVDD_ZONEA_ISL69260_ADDR (0xC4 >> 1) |
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#define | VR_ASIC_P1V8_VPP_HBM0_HBM2_HBM4_MP2971_ADDR (0xE6 >> 1) |
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#define | VR_ASIC_P1V8_VPP_HBM0_HBM2_HBM4_ISL69260_ADDR (0xC4 >> 1) |
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#define | VR_ASIC_P0V75_TRVDD_ZONEB_MP2971_ADDR (0xEC >> 1) |
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#define | VR_ASIC_P0V75_TRVDD_ZONEB_ISL69260_ADDR (0xC6 >> 1) |
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#define | VR_ASIC_P0V4_VDDQL_HBM0_HBM2_HBM4_MP2971_ADDR (0xEC >> 1) |
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#define | VR_ASIC_P0V4_VDDQL_HBM0_HBM2_HBM4_ISL69260_ADDR (0xC6 >> 1) |
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#define | VR_ASIC_P1V1_VDDC_HBM0_HBM2_HBM4_MP2971_ADDR (0xEA >> 1) |
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#define | VR_ASIC_P1V1_VDDC_HBM0_HBM2_HBM4_ISL69260_ADDR (0xE8 >> 1) |
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#define | VR_ASIC_P0V75_VDDPHY_HBM0_HBM2_HBM4_MP2971_ADDR (0xEA >> 1) |
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#define | VR_ASIC_P0V75_VDDPHY_HBM0_HBM2_HBM4_ISL69260_ADDR (0xE8 >> 1) |
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#define | VR_ASIC_P0V9_TRVDD_ZONEA_MP2971_ADDR (0xE4 >> 1) |
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#define | VR_ASIC_P0V9_TRVDD_ZONEA_ISL69260_ADDR (0xC0 >> 1) |
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#define | VR_ASIC_P1V8_VPP_HBM1_HBM3_HBM5_MP2971_ADDR (0xE4 >> 1) |
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#define | VR_ASIC_P1V8_VPP_HBM1_HBM3_HBM5_ISL69260_ADDR (0xC0 >> 1) |
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#define | VR_ASIC_P0V9_TRVDD_ZONEB_MP2971_ADDR (0xE8 >> 1) |
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#define | VR_ASIC_P0V9_TRVDD_ZONEB_ISL69260_ADDR (0xC2 >> 1) |
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#define | VR_ASIC_P0V4_VDDQL_HBM1_HBM3_HBM5_MP2971_ADDR (0xE8 >> 1) |
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#define | VR_ASIC_P0V4_VDDQL_HBM1_HBM3_HBM5_ISL69260_ADDR (0xC2 >> 1) |
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#define | VR_ASIC_P1V1_VDDC_HBM1_HBM3_HBM5_MP2971_ADDR (0xEE >> 1) |
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#define | VR_ASIC_P1V1_VDDC_HBM1_HBM3_HBM5_ISL69260_ADDR (0xC4 >> 1) |
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#define | VR_ASIC_P0V75_VDDPHY_HBM1_HBM3_HBM5_MP2971_ADDR (0xEE >> 1) |
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#define | VR_ASIC_P0V75_VDDPHY_HBM1_HBM3_HBM5_ISL69260_ADDR (0xC4 >> 1) |
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#define | VR_ASIC_P0V8_VDDA_PCIE_MP2971_ADDR (0xF2 >> 1) |
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#define | VR_ASIC_P0V8_VDDA_PCIE_MP2971_FAB3_ADDR (0xD2 >> 1) |
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#define | VR_ASIC_P0V8_VDDA_PCIE_ISL69260_ADDR (0xC6 >> 1) |
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#define | VR_ASIC_P1V2_VDDHTX_PCIE_MP2971_ADDR (0xF2 >> 1) |
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#define | VR_ASIC_P1V2_VDDHTX_PCIE_MP2971_FAB3_ADDR (0xD2 >> 1) |
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#define | VR_ASIC_P1V2_VDDHTX_PCIE_ISL69260_ADDR (0xC6 >> 1) |
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#define | UBC1_P12V_TEMP_C 0x01 |
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#define | UBC1_P50V_INPUT_VOLT_V 0x02 |
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#define | UBC1_P12V_OUTPUT_VOLT_V 0x03 |
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#define | UBC1_P12V_CURR_A 0x04 |
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#define | UBC1_P12V_PWR_W 0x05 |
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#define | UBC2_P12V_TEMP_C 0x06 |
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#define | UBC2_P50V_INPUT_VOLT_V 0x07 |
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#define | UBC2_P12V_OUTPUT_VOLT_V 0x08 |
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#define | UBC2_P12V_CURR_A 0x09 |
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#define | UBC2_P12V_PWR_W 0x0A |
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#define | TOP_INLET_TEMP_C 0x0B |
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#define | TOP_OUTLET_TEMP_C 0x0C |
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#define | BOT_INLET_TEMP_C 0x0D |
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#define | BOT_OUTLET_TEMP_C 0x0E |
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#define | ASIC_DIE_ATH_SENSOR_0_TEMP_C 0x0F |
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#define | ASIC_DIE_ATH_SENSOR_1_TEMP_C 0x10 |
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#define | ASIC_DIE_N_OWL_TEMP_C 0x11 |
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#define | ASIC_DIE_S_OWL_TEMP_C 0x12 |
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#define | VR_P3V3_TEMP_C 0x13 |
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#define | VR_P3V3_VOLT_V 0x14 |
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#define | VR_P3V3_CURR_A 0x15 |
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#define | VR_P3V3_PWR_W 0x16 |
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#define | VR_ASIC_P0V85_PVDD_TEMP_C 0x17 |
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#define | VR_ASIC_P0V85_PVDD_VOLT_V 0x18 |
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#define | VR_ASIC_P0V85_PVDD_CURR_A 0x19 |
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#define | VR_ASIC_P0V85_PVDD_PWR_W 0x1A |
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#define | VR_ASIC_P0V75_PVDD_CH_N_TEMP_C 0x1B |
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#define | VR_ASIC_P0V75_PVDD_CH_N_VOLT_V 0x1C |
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#define | VR_ASIC_P0V75_PVDD_CH_N_CURR_A 0x1D |
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#define | VR_ASIC_P0V75_PVDD_CH_N_PWR_W 0x1E |
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#define | VR_ASIC_P0V75_MAX_PHY_N_TEMP_C 0x1F |
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#define | VR_ASIC_P0V75_MAX_PHY_N_VOLT_V 0x20 |
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#define | VR_ASIC_P0V75_MAX_PHY_N_CURR_A 0x21 |
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#define | VR_ASIC_P0V75_MAX_PHY_N_PWR_W 0x22 |
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#define | VR_ASIC_P0V75_PVDD_CH_S_TEMP_C 0x23 |
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#define | VR_ASIC_P0V75_PVDD_CH_S_VOLT_V 0x24 |
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#define | VR_ASIC_P0V75_PVDD_CH_S_CURR_A 0x25 |
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#define | VR_ASIC_P0V75_PVDD_CH_S_PWR_W 0x26 |
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#define | VR_ASIC_P0V75_MAX_PHY_S_TEMP_C 0x27 |
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#define | VR_ASIC_P0V75_MAX_PHY_S_VOLT_V 0x28 |
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#define | VR_ASIC_P0V75_MAX_PHY_S_CURR_A 0x29 |
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#define | VR_ASIC_P0V75_MAX_PHY_S_PWR_W 0x2A |
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#define | VR_ASIC_P0V75_TRVDD_ZONEA_TEMP_C 0x2B |
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#define | VR_ASIC_P0V75_TRVDD_ZONEA_VOLT_V 0x2C |
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#define | VR_ASIC_P0V75_TRVDD_ZONEA_CURR_A 0x2D |
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#define | VR_ASIC_P0V75_TRVDD_ZONEA_PWR_W 0x2E |
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#define | VR_ASIC_P1V8_VPP_HBM0_HBM2_HBM4_TEMP_C 0x2F |
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#define | VR_ASIC_P1V8_VPP_HBM0_HBM2_HBM4_VOLT_V 0x30 |
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#define | VR_ASIC_P1V8_VPP_HBM0_HBM2_HBM4_CURR_A 0x31 |
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#define | VR_ASIC_P1V8_VPP_HBM0_HBM2_HBM4_PWR_W 0x32 |
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#define | VR_ASIC_P0V75_TRVDD_ZONEB_TEMP_C 0x33 |
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#define | VR_ASIC_P0V75_TRVDD_ZONEB_VOLT_V 0x34 |
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#define | VR_ASIC_P0V75_TRVDD_ZONEB_CURR_A 0x35 |
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#define | VR_ASIC_P0V75_TRVDD_ZONEB_PWR_W 0x36 |
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#define | VR_ASIC_P0V4_VDDQL_HBM0_HBM2_HBM4_TEMP_C 0x37 |
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#define | VR_ASIC_P0V4_VDDQL_HBM0_HBM2_HBM4_VOLT_V 0x38 |
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#define | VR_ASIC_P0V4_VDDQL_HBM0_HBM2_HBM4_CURR_A 0x39 |
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#define | VR_ASIC_P0V4_VDDQL_HBM0_HBM2_HBM4_PWR_W 0x3A |
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#define | VR_ASIC_P1V1_VDDC_HBM0_HBM2_HBM4_TEMP_C 0x3B |
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#define | VR_ASIC_P1V1_VDDC_HBM0_HBM2_HBM4_VOLT_V 0x3C |
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#define | VR_ASIC_P1V1_VDDC_HBM0_HBM2_HBM4_CURR_A 0x3D |
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#define | VR_ASIC_P1V1_VDDC_HBM0_HBM2_HBM4_PWR_W 0x3E |
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#define | VR_ASIC_P0V75_VDDPHY_HBM0_HBM2_HBM4_TEMP_C 0x3F |
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#define | VR_ASIC_P0V75_VDDPHY_HBM0_HBM2_HBM4_VOLT_V 0x40 |
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#define | VR_ASIC_P0V75_VDDPHY_HBM0_HBM2_HBM4_CURR_A 0x41 |
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#define | VR_ASIC_P0V75_VDDPHY_HBM0_HBM2_HBM4_PWR_W 0x42 |
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#define | VR_ASIC_P0V9_TRVDD_ZONEA_TEMP_C 0x43 |
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#define | VR_ASIC_P0V9_TRVDD_ZONEA_VOLT_V 0x44 |
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#define | VR_ASIC_P0V9_TRVDD_ZONEA_CURR_A 0x45 |
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#define | VR_ASIC_P0V9_TRVDD_ZONEA_PWR_W 0x46 |
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#define | VR_ASIC_P1V8_VPP_HBM1_HBM3_HBM5_TEMP_C 0x47 |
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#define | VR_ASIC_P1V8_VPP_HBM1_HBM3_HBM5_VOLT_V 0x48 |
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#define | VR_ASIC_P1V8_VPP_HBM1_HBM3_HBM5_CURR_A 0x49 |
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#define | VR_ASIC_P1V8_VPP_HBM1_HBM3_HBM5_PWR_W 0x4A |
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#define | VR_ASIC_P0V9_TRVDD_ZONEB_TEMP_C 0x4B |
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#define | VR_ASIC_P0V9_TRVDD_ZONEB_VOLT_V 0x4C |
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#define | VR_ASIC_P0V9_TRVDD_ZONEB_CURR_A 0x4D |
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#define | VR_ASIC_P0V9_TRVDD_ZONEB_PWR_W 0x4E |
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#define | VR_ASIC_P0V4_VDDQL_HBM1_HBM3_HBM5_TEMP_C 0x4F |
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#define | VR_ASIC_P0V4_VDDQL_HBM1_HBM3_HBM5_VOLT_V 0x50 |
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#define | VR_ASIC_P0V4_VDDQL_HBM1_HBM3_HBM5_CURR_A 0x51 |
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#define | VR_ASIC_P0V4_VDDQL_HBM1_HBM3_HBM5_PWR_W 0x52 |
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#define | VR_ASIC_P1V1_VDDC_HBM1_HBM3_HBM5_TEMP_C 0x53 |
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#define | VR_ASIC_P1V1_VDDC_HBM1_HBM3_HBM5_VOLT_V 0x54 |
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#define | VR_ASIC_P1V1_VDDC_HBM1_HBM3_HBM5_CURR_A 0x55 |
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#define | VR_ASIC_P1V1_VDDC_HBM1_HBM3_HBM5_PWR_W 0x56 |
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#define | VR_ASIC_P0V75_VDDPHY_HBM1_HBM3_HBM5_TEMP_C 0x57 |
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#define | VR_ASIC_P0V75_VDDPHY_HBM1_HBM3_HBM5_VOLT_V 0x58 |
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#define | VR_ASIC_P0V75_VDDPHY_HBM1_HBM3_HBM5_CURR_A 0x59 |
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#define | VR_ASIC_P0V75_VDDPHY_HBM1_HBM3_HBM5_PWR_W 0x5A |
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#define | VR_ASIC_P0V8_VDDA_PCIE_TEMP_C 0x5B |
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#define | VR_ASIC_P0V8_VDDA_PCIE_VOLT_V 0x5C |
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#define | VR_ASIC_P0V8_VDDA_PCIE_CURR_A 0x5D |
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#define | VR_ASIC_P0V8_VDDA_PCIE_PWR_W 0x5E |
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#define | VR_ASIC_P1V2_VDDHTX_PCIE_TEMP_C 0x5F |
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#define | VR_ASIC_P1V2_VDDHTX_PCIE_VOLT_V 0x60 |
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#define | VR_ASIC_P1V2_VDDHTX_PCIE_CURR_A 0x61 |
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#define | VR_ASIC_P1V2_VDDHTX_PCIE_PWR_W 0x62 |
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#define | TMP75_TEMP_OFFSET 0x00 |
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#define | UPDATE_INTERVAL_1S 1 |
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#define | UPDATE_INTERVAL_5S 5 |
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#define | UPDATE_INTERVAL_60S 60 |
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