ads112c.h File Reference

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Classes
struct	_ads112c_init_arg

Macros
#define	CMD_RESET   0x06
#define	CMD_START_SYNC   0x08
#define	CMD_POWERDOWN   0x02
#define	CMD_RDATA   0x10
#define	CMD_RREG   0x20
#define	CMD_WREG   0x40
#define	CFG_REG_OFFSET0   0x00
#define	CFG_REG_OFFSET1   0x04
#define	CFG_REG_OFFSET2   0x08
#define	CFG_REG_OFFSET3   0x0C
#define	ADS112C_REG2_DRDY_READY   0x80
#define	ENABLE_RESET_CFG_REG   1
#define	DISABLE_RESET_CFG_REG   0

Typedefs
typedef struct _ads112c_init_arg	ads112c_init_arg

Enumerations
enum	ADS112C_REG0_CONFIG {   ADS112C_REG0_INPUT_AIN0AIN1 = 0x00 , ADS112C_REG0_INPUT_AIN0AIN2 = 0x10 , ADS112C_REG0_INPUT_AIN0AIN3 = 0x20 , ADS112C_REG0_INPUT_AIN1AIN0 = 0x30 ,   ADS112C_REG0_INPUT_AIN1AIN2 = 0x40 , ADS112C_REG0_INPUT_AIN1AIN3 = 0x50 , ADS112C_REG0_INPUT_AIN2AIN3 = 0x60 , ADS112C_REG0_INPUT_AIN3AIN2 = 0x70 ,   ADS112C_REG0_INPUT_AIN0AVSS = 0x80 , ADS112C_REG0_INPUT_AIN1AVSS = 0x90 , ADS112C_REG0_INPUT_AIN2AVSS = 0xA0 , ADS112C_REG0_INPUT_AIN3AVSS = 0xB0 ,   ADS112C_REG0_GAIN1 = 0x00 , ADS112C_REG0_GAIN2 = 0x02 , ADS112C_REG0_GAIN4 = 0x04 , ADS112C_REG0_GAIN8 = 0x06 ,   ADS112C_REG0_GAIN16 = 0x08 , ADS112C_REG0_GAIN32 = 0x0A , ADS112C_REG0_GAIN64 = 0x0C , ADS112C_REG0_GAIN128 = 0x0E ,   ADS112C_REG0_PGA_ENABLE = 0x00 , ADS112C_REG0_PGA_DISABLE = 0x01 }
enum	ADS112C_REG1_CONFIG {   ADS112C_REG1_DR_1000_SPS = 0xC0 , ADS112C_REG1_SINGLEMODE = 0x00 , ADS112C_REG1_CONTINUEMODE = 0x08 , ADS112C_REG1_INTERNALV = 0x00 ,   ADS112C_REG1_EXTERNALV = 0x02 , ADS112C_REG1_TEMPMODE_DISABLE = 0x00 , ADS112C_REG1_TEMPMODE_ENABLE = 0x01 }
enum	ADS112C_REG2_CONFIG {   ADS112C_REG2_IDAC_OFF = 0x00 , ADS112C_REG2_IDAC_10UA = 0x01 , ADS112C_REG2_IDAC_50UA = 0x02 , ADS112C_REG2_IDAC_100UA = 0x03 ,   ADS112C_REG2_IDAC_250UA = 0x04 , ADS112C_REG2_IDAC_500UA = 0x05 , ADS112C_REG2_IDAC_1000UA = 0x06 , ADS112C_REG2_IDAC_1500UA = 0x07 }
enum	ADS112C_REG3_CONFIG {   ADS112C_REG3_IDAC1_DISABLED = 0x00 , ADS112C_REG3_IDAC1_AIN0 = 0x20 , ADS112C_REG3_IDAC1_AIN1 = 0x40 , ADS112C_REG3_IDAC1_AIN2 = 0x60 ,   ADS112C_REG3_IDAC1_AIN3 = 0x80 , ADS112C_REG3_IDAC1_REFP = 0xA0 , ADS112C_REG3_IDAC1_REFN = 0xC0 , ADS112C_REG3_IDAC1_RESERVED = 0xE0 }
enum	ADS112C_READ_OUTPUT_OFFSET { ADS112C_READ_OUTPUT_RAW = 0x00 , ADS112C_READ_OUTPUT_VOLT = 0x01 , ADS112C_READ_OUTPUT_TEMP = 0x02 }

Macro Definition Documentation

ADS112C_REG2_DRDY_READY

#define ADS112C_REG2_DRDY_READY   0x80

CFG_REG_OFFSET0

#define CFG_REG_OFFSET0   0x00

CFG_REG_OFFSET1

#define CFG_REG_OFFSET1   0x04

CFG_REG_OFFSET2

#define CFG_REG_OFFSET2   0x08

CFG_REG_OFFSET3

#define CFG_REG_OFFSET3   0x0C

CMD_POWERDOWN

#define CMD_POWERDOWN   0x02

CMD_RDATA

#define CMD_RDATA   0x10

CMD_RESET

#define CMD_RESET   0x06

CMD_RREG

#define CMD_RREG   0x20

CMD_START_SYNC

#define CMD_START_SYNC   0x08

CMD_WREG

#define CMD_WREG   0x40

DISABLE_RESET_CFG_REG

#define DISABLE_RESET_CFG_REG   0

ENABLE_RESET_CFG_REG

#define ENABLE_RESET_CFG_REG   1

Typedef Documentation

ads112c_init_arg

typedef struct _ads112c_init_arg ads112c_init_arg

Enumeration Type Documentation

ADS112C_READ_OUTPUT_OFFSET

enum ADS112C_READ_OUTPUT_OFFSET

Enumerator
ADS112C_READ_OUTPUT_RAW
ADS112C_READ_OUTPUT_VOLT
ADS112C_READ_OUTPUT_TEMP

ADS112C_REG0_CONFIG

enum ADS112C_REG0_CONFIG

Enumerator
ADS112C_REG0_INPUT_AIN0AIN1
ADS112C_REG0_INPUT_AIN0AIN2
ADS112C_REG0_INPUT_AIN0AIN3
ADS112C_REG0_INPUT_AIN1AIN0
ADS112C_REG0_INPUT_AIN1AIN2
ADS112C_REG0_INPUT_AIN1AIN3
ADS112C_REG0_INPUT_AIN2AIN3
ADS112C_REG0_INPUT_AIN3AIN2
ADS112C_REG0_INPUT_AIN0AVSS
ADS112C_REG0_INPUT_AIN1AVSS
ADS112C_REG0_INPUT_AIN2AVSS
ADS112C_REG0_INPUT_AIN3AVSS
ADS112C_REG0_GAIN1
ADS112C_REG0_GAIN2
ADS112C_REG0_GAIN4
ADS112C_REG0_GAIN8
ADS112C_REG0_GAIN16
ADS112C_REG0_GAIN32
ADS112C_REG0_GAIN64
ADS112C_REG0_GAIN128
ADS112C_REG0_PGA_ENABLE
ADS112C_REG0_PGA_DISABLE

ADS112C_REG1_CONFIG

enum ADS112C_REG1_CONFIG

Enumerator
ADS112C_REG1_DR_1000_SPS
ADS112C_REG1_SINGLEMODE
ADS112C_REG1_CONTINUEMODE
ADS112C_REG1_INTERNALV
ADS112C_REG1_EXTERNALV
ADS112C_REG1_TEMPMODE_DISABLE
ADS112C_REG1_TEMPMODE_ENABLE

ADS112C_REG2_CONFIG

enum ADS112C_REG2_CONFIG

Enumerator
ADS112C_REG2_IDAC_OFF
ADS112C_REG2_IDAC_10UA
ADS112C_REG2_IDAC_50UA
ADS112C_REG2_IDAC_100UA
ADS112C_REG2_IDAC_250UA
ADS112C_REG2_IDAC_500UA
ADS112C_REG2_IDAC_1000UA
ADS112C_REG2_IDAC_1500UA

ADS112C_REG3_CONFIG

enum ADS112C_REG3_CONFIG

Enumerator
ADS112C_REG3_IDAC1_DISABLED
ADS112C_REG3_IDAC1_AIN0
ADS112C_REG3_IDAC1_AIN1
ADS112C_REG3_IDAC1_AIN2
ADS112C_REG3_IDAC1_AIN3
ADS112C_REG3_IDAC1_REFP
ADS112C_REG3_IDAC1_REFN
ADS112C_REG3_IDAC1_RESERVED