17#ifndef PLAT_IRIS_SMBUS_H
18#define PLAT_IRIS_SMBUS_H
23#define FASTBOOT_MODE BIT(0)
24#define CMRT_SIC_MODE BIT(1)
25#define RECOVERY_MODE BIT(2)
30#define HAMSA_BOOT1_ASIC_MEM_ADDR 0x94008000
31#define HAMSA_BOOT1_ADDR 0x32
34#define SMBUS_MAX_PKT_LEN 32
36#define SMBUS_MAX_PAYLOAD_LEN 24
38#define MSG_PKT_LEN_OFFSET 0
39#define MSG_ADDR_OFFSET 1
40#define ADDRESS_BYTE_SZ 4
41#define DATA_LEN_BYTE_SZ 1
42#define MSG_DATA_LEN_OFFSET 5
43#define MSG_RDWR_DATA_START 6
44#define BYTES_PER_WORD 4
45#define PKT_LEN_BYTE_SZ 1
47#define ADDR_DATA_LEN_SZ (ADDRESS_BYTE_SZ + DATA_LEN_BYTE_SZ)
51#define FW_DL_START BIT(7)
52#define FW_DL_SLV_RDY BIT(6)
53#define FW_DL_HST_ABRT BIT(5)
54#define FW_DL_SLV_ABRTD BIT(4)
55#define FW_DL_FINISH BIT(3)
56#define FW_DL_SLV_DONE BIT(2)
57#define FW_DL_SLV_PROG BIT(1)
58#define FW_SB_EXIT_CMD BIT(0)
60#define MEDHA0_I2C_ADDR 0x33
61#define MEDHA1_I2C_ADDR 0x34
62#define OWLW_I2C_ADDR 0x6E
63#define OWLE_I2C_ADDR 0x6E
65#define MAX_DATA_PKT_SIZE 24
66#define STATUS_RETRY_CNT 2
67#define ERROR_CODE_LEN 8
70#define SMBUS_ERROR 122
74#define MODULE_ERROR 124
76#define FW_SMBUS_ERROR 130
78#define SB_MODE_QUERY 135
80#define FW_CTRL_WRITE 136
82#define FW_CTRL_READ 137
84#define FW_DATA_WRITE 138
int iris_smbus_fast_boot(uint8_t *image_buff, uint32_t img_dest_addr, uint32_t img_size)