24#define BIC_FW_DATA_LENGTH 7
25#define PCIE_CARD_NOT_PRESENT 0
26#define PCIE_CARD_PRESENT 1
27#define PCIE_CARD_ID_OFFSET 30
29#define PCIE_CARD_NOT_PRESENT_BIT BIT(0)
30#define PCIE_CARD_NOT_ACCESSIABLE_BIT BIT(1)
31#define PCIE_CARD_DEVICE_NOT_READY_BIT BIT(2)
33#define IS_SECTOR_END_MASK 0x80
34#define WITHOUT_SENCTOR_END_MASK 0x7F
35#define BIC_UPDATE_MAX_OFFSET 0x50000
36#define PM8702_UPDATE_MAX_OFFSET 0x150000
37#define PM8702_INITIATE_FW_OFFSET 0x0000
39#define PM8702_DEFAULT_NEXT_ACTIVE_SLOT 0
40#define PM8702_NO_HBO_RUN_VAL 0
41#define PM8702_TRANSFER_FW_DATA_LEN 128
42#define PM8702_RETURN_SUCCESS 0x00
43#define PM8702_BUSY_DELAY_MS 100
44#define PM8702_TRANSFER_DELAY_MS 20
45#define PM8702_TRANSFER_FW_HEADER_LEN 128
void pal_construct_ipmi_add_sel_msg(ipmi_msg *msg, common_addsel_msg_t *sel_msg)
Definition: plat_ipmi.c:55
CXL_FRU_OPTIONAL
Definition: plat_ipmi.h:86
@ CXL_FRU_WRITE
Definition: plat_ipmi.h:87
@ CXL_FRU_READ
Definition: plat_ipmi.h:88
MC_FIRMWARE_COMPONENT
Definition: plat_ipmi.h:48
@ MC_COMPNT_CXL5
Definition: plat_ipmi.h:55
@ MC_COMPNT_CXL6_VR_P0V89A
Definition: plat_ipmi.h:74
@ MC_COMPNT_MAX
Definition: plat_ipmi.h:83
@ MC_COMPNT_CXL8_VR_VR_PVDDQ_CD
Definition: plat_ipmi.h:82
@ MC_COMPNT_CXL4_VR_P0V89A
Definition: plat_ipmi.h:68
@ MC_COMPNT_CXL2_VR_P0V8D_PVDDQ_AB
Definition: plat_ipmi.h:63
@ MC_COMPNT_CXL7_VR_VR_PVDDQ_CD
Definition: plat_ipmi.h:79
@ MC_COMPNT_CXL7_VR_P0V89A
Definition: plat_ipmi.h:77
@ MC_COMPNT_CXL6_VR_P0V8D_PVDDQ_AB
Definition: plat_ipmi.h:75
@ MC_COMPNT_CXL5_VR_P0V89A
Definition: plat_ipmi.h:71
@ MC_COMPNT_CXL2_VR_P0V89A
Definition: plat_ipmi.h:62
@ MC_COMPNT_CXL4_VR_VR_PVDDQ_CD
Definition: plat_ipmi.h:70
@ MC_COMPNT_BIC
Definition: plat_ipmi.h:49
@ MC_COMPNT_CXL1_VR_P0V89A
Definition: plat_ipmi.h:59
@ MC_COMPNT_CXL3_VR_VR_PVDDQ_CD
Definition: plat_ipmi.h:67
@ MC_COMPNT_CXL8
Definition: plat_ipmi.h:58
@ MC_COMPNT_CXL2_VR_VR_PVDDQ_CD
Definition: plat_ipmi.h:64
@ MC_COMPNT_CXL7_VR_P0V8D_PVDDQ_AB
Definition: plat_ipmi.h:78
@ MC_COMPNT_CXL6_VR_VR_PVDDQ_CD
Definition: plat_ipmi.h:76
@ MC_COMPNT_CXL5_VR_P0V8D_PVDDQ_AB
Definition: plat_ipmi.h:72
@ MC_COMPNT_CXL4
Definition: plat_ipmi.h:54
@ MC_COMPNT_CXL6
Definition: plat_ipmi.h:56
@ MC_COMPNT_CXL3_VR_P0V8D_PVDDQ_AB
Definition: plat_ipmi.h:66
@ MC_COMPNT_CXL5_VR_VR_PVDDQ_CD
Definition: plat_ipmi.h:73
@ MC_COMPNT_CXL3
Definition: plat_ipmi.h:53
@ MC_COMPNT_CPLD
Definition: plat_ipmi.h:50
@ MC_COMPNT_CXL2
Definition: plat_ipmi.h:52
@ MC_COMPNT_CXL7
Definition: plat_ipmi.h:57
@ MC_COMPNT_CXL4_VR_P0V8D_PVDDQ_AB
Definition: plat_ipmi.h:69
@ MC_COMPNT_CXL3_VR_P0V89A
Definition: plat_ipmi.h:65
@ MC_COMPNT_CXL1_VR_VR_PVDDQ_CD
Definition: plat_ipmi.h:61
@ MC_COMPNT_CXL1
Definition: plat_ipmi.h:51
@ MC_COMPNT_CXL1_VR_P0V8D_PVDDQ_AB
Definition: plat_ipmi.h:60
@ MC_COMPNT_CXL8_VR_P0V89A
Definition: plat_ipmi.h:80
@ MC_COMPNT_CXL8_VR_P0V8D_PVDDQ_AB
Definition: plat_ipmi.h:81