OpenBIC
OpenSource Bridge-IC
pmic.h
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1/*
2 * Copyright (c) Meta Platforms, Inc. and affiliates.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef PMIC_H
18#define PMIC_H
19
20#include <stdio.h>
21#include <stdint.h>
22#include <string.h>
23
24//Memory write read request max data len
25#define MAX_MEMORY_DATA 32
26
27//PMIC write/read data len
28#define PMIC_WRITE_DATA_LEN 14
29#define PMIC_READ_DATA_LEN 12
30
31//PMIC write/read memory command
32#define CMD_SMBUS_READ_MEMORY 0x47
33#define CMD_SMBUS_WRITE_MEMORY 0x48
34
35//PMIC report power/total mode setting
36#define SET_DEV_REPORT_POWER 0x45
37#define SET_DEV_REPORT_TOTAL 0xC2
38
39//PMIC total/power/ADC/record register address value
40#define PMIC_TOTAL_INDIV_ADDR_VAL 0x0000001A
41#define PMIC_PWR_CURR_ADDR_VAL 0x0000001B
42#define PMIC_ADC_ADDR_VAL 0x00000030
43#define PMIC_SWA_ADDR_VAL 0x0000000C
44#define PMIC_POR_ERROR_LOG_ADDR_VAL 0x00000005
45
46//PMIC enable ADC bit
47#define PMIC_ENABLE_ADC_BIT BIT(7)
48
49//PMIC PMIC setting delay msec
50#define PMIC_COMMAND_DELAY_MSEC 250
51
52//Send PMIC memory write read parameter
53#define INTEL_ID 0x00000157
54#define PMIC_ADDR_SIZE 0x1
55#define PMIC_DATA_LEN 0x1
56
57//PMIC total power uint
58#define PMIC_TOTAL_POWER_MW 125
59
61 uint32_t intel_id;
64 uint8_t addr_size;
65 uint8_t data_len;
66 uint32_t addr_value;
69
70extern uint8_t *compose_memory_write_read_req(uint8_t smbus_identifier, uint8_t smbus_address,
71 uint32_t addr_value, uint8_t *write_data,
72 uint8_t write_len);
73extern int pmic_ipmb_transfer(int *total_pmic_power, uint8_t seq_source, uint8_t netFn,
74 uint8_t command, uint8_t source_inft, uint8_t target_inft,
75 uint16_t data_len, uint8_t *data);
76int pal_set_pmic_error_flag(uint8_t dimm_id, uint8_t error_type);
77
78#endif
uint8_t seq_source
Definition: ipmb.h:5
uint16_t data_len
Definition: ipmb.h:14
uint8_t data[]
Definition: isl69259.c:2
struct _memory_write_read_req_ memory_write_read_req
#define MAX_MEMORY_DATA
Definition: pmic.h:25
int pmic_ipmb_transfer(int *total_pmic_power, uint8_t seq_source, uint8_t netFn, uint8_t command, uint8_t source_inft, uint8_t target_inft, uint16_t data_len, uint8_t *data)
Definition: pmic.c:54
int pal_set_pmic_error_flag(uint8_t dimm_id, uint8_t error_type)
Definition: pmic.c:167
uint8_t * compose_memory_write_read_req(uint8_t smbus_identifier, uint8_t smbus_address, uint32_t addr_value, uint8_t *write_data, uint8_t write_len)
Definition: pmic.c:29
Definition: pmic.h:60
uint8_t write_data[MAX_MEMORY_DATA]
Definition: pmic.h:67
uint8_t data_len
Definition: pmic.h:65
uint8_t smbus_identifier
Definition: pmic.h:62
uint8_t addr_size
Definition: pmic.h:64
uint32_t intel_id
Definition: pmic.h:61
uint8_t smbus_address
Definition: pmic.h:63
uint32_t addr_value
Definition: pmic.h:66